LOW POWER REALIZATION OF NETWORK INTERFACE ROUTER

The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the Five port router using the latest verification methodologies and Hardware Verification Languages. In the proposed design the FSM is designed with reduced number of states. Due to reduction of states the amount of time to produce the response became less obviously the frequency is improved. At the same time the memory required to design of this Router chip is also reduced. In the existed design number of LUTS are 724. In the existed design the total memory usage is 297148 kilobytes and the maximum frequency is 76.374MHz, whereas in the proposed design the number of LUTS are 240.In the proposed design, the total memory usage is 249164 kilobytes and the maximum frequency is 81.162MHz

VLSI ENHANCEMENT OF AREA OPTIMIZED FLEXIBLE ARCHITECTURE SUPPORTING SYMMETRIC CRYPTOGRAPHY

Data encryption (cryptography) is utilized in various applications and environments. The specific utilization of encryption and the implementation of the AES will be based on many factors particular to the computer system and its associated components. Communication security provides protection to data by enciphering it at the transmitting point and deciphering it at the receiving point. File security provides protection to data by enciphering it when it is recorded on a storage medium and deciphering it when it is read back from the storage medium. In the proposed design the security method uses symmetric Cryptography technique which provides same keys to sender and receiver to transfer the information for reducing the design complexity. The transferred information is stored in the memory unit for further using it or for further processing using low cost buffer element. Transmission cables are used to provide communication between the connected devices. Control logic is used to provide the patters for transmission through crypto unit

LOW COMPLEXITY D LATCH BASED CSLA FOR SPEED CRITICAL APPLICATIONS

The Carry Select Adder is used in many systems to relieve the problem of carry propagation delay which is happen by independently generating multiple carries and to generate the sum then select a carry. Due to uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input However, the CSLA is not time efficient, then by the multiplexers the final sum and carry are selected. The basic idea of this work is to achieve high speed and low power consumption by use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA. At the same time to further reduce the power consumption, a new approach of CSLA with D LATCH is proposed in this project. In the proposed scheme, before the calculation of-final-sum the carry select that is specified as CS operation is scheduled. For logic optimization of Carry selection bit patterns of two anticipating carry words that is corresponding to cin = 0 and 1 and fixed cin bits are used. Using optimized logic units an efficient CSLA design is obtained. The proposed Carry Select Adder design involves significantly less area and power than the recently proposed BEC-based CSLA