Detección automática de faltas empleando lógica borrosa

Presentamos a continuación una herramienta para la detección y clasificación de faltas en circuitos analógicos a partir de un reducido conjunto de medidas. Se emplea una estructura formada por neuronas borrosas, que permite el reconocimiento de regiones de clasificación de forma arbitraria. Permitiendo la realización de tests tanto funcionales como paramétricos

Selección automática de topologías

Se presenta una herramienta para la selección de topologías a partir de unas especificaciones de entre un conjunto de topologías alternativas fijas empleando lógica borrosa. Las reglas de decisión empleadas pueden proceder del conocimiento de un diseñador experto o ser generadas automáticamente mediante un procedimiento de aprendizaje a partir de los resultados de la optimización de una rejilla de especificaciones. Se muestran una serie de ejemplos que reflejan la capacidad de la herramienta para aprender la elección de celdas analógicas

A collection of fuzzy logic-based tools for the automated design, modelling and test of analog circuits

We have developed a collection of tools for the design, modeling, and test of analog circuits. Sharing a common fuzzy-logic based framework, the tools are part of FASY (Fuzzy-Logic-Based Analog Synthesis), an analog design package developed at the University of Seville. The first tool uses fuzzy logic for topology selection of analog cells. It follows decision rules directly entered by a human expert or automatically generated from its experience with earlier designs. Second, a performance-modeling tool provides a qualitative description of a circuit's behavior. Alternatively, it can use a learning process to accurately model circuit performance. Finally, an analog testing tool uses a fuzzy-neuron classifier to detect and classify faults in analog circuits

Time domain analysis of partial discharges envelope in medium voltage XLPE cables

Partial discharge (PD) analysis has been widely used to detect premature degradation of power cables. Although there are recognized techniques for PD analysis, there is still lack of knowledge about measuring and modeling this phenomenon. This paper proposes a new model based on time domain parameters of the PD signal envelope. The proposed variables (time duration, and rising and falling slopes of the envelopes), together with conventional PD analyses focused on PD amplitude and phase resolved patterns, will provide a better understanding of this phenomenon. Based on this model, a new technique to reshape the PD signal envelope is also proposed that compensates the negative effect of dispersion in the location techniques that estimate the time of arrival (TOA). Experimental results were obtained in the lab, where a power cable has been artificially damaged in order to produce PD. To this end, a specific PD on-line acquisition system has been developed. In the first set of experiments, we illustrate how the cable attenuates and disperses the PD signal envelope. In the second one, we show how the proposed variables are useful to distinguish among different types of PD sources. Finally, an accurate estimation of the PD source location is achieved by measuring the time of arrival of the PD signal envelopes at both cable ends, and reshaping one of the signals captured. This technique improves the accuracy of the estimated location of the PD sources, both in simulation and in experimental results

Modeling Airfield Ground Lighting Systems for Narrowband Power-Line Communications

Airfield ground lighting (AGL) systems are responsible for providing visual reference to aircrafts in the airport neighborhood. In an AGL system, a large number of lamps are organized in serial circuits and connected to current regulators that supply energy to the lamps. Controlling and monitoring lamps (including detection and location of burnt-out lamps) are critical for cost-saving maintenance and operation of AGL systems. Power-line Communications (PLC) is an attractive technology to connect elements of the AGL, reusing the power distribution cable as a transmission medium. PLC technologies avoid the installation of new wires throughout the airport infrastructure. This paper proposes a new model for power-line communication links in AGL systems. Every element (isolation transformer, primary circuit cable, and lamps) has been analyzed in laboratory and modeled using SPICE. The resulting models have been integrated to build a complete power-line link model. Simulation results are compared to experimental results obtained in real conditions in the Airport of Seville (Spain)

Adquisición de datos digitales con protocolo VME sobre FPGA

En este artículo se presenta la realización sobre FPGA de un circuito con 16 filtros digitales. Un cambio en la entrada es validado cada vez que tres muestras consecutivas toman el mismo valor. El dato muestreado es accesible mediante protocolo VME estándar, incluyendo daisy-cbain para la gestión de interrupciones. El circuito de acceso VME se ha descrito en lenguaje de comportamiento VERILOG-XL, y sintetizado usando SYNERGY. El resto del circuito ha sido capturado y simulado empleando el entorno de diseño Framework II de Cadence. El circuito ha sido programado en una FPGA 1020A de Texas Instrument. Como resultado se ha obtenido una tarjeta de adquisición de datos con una densidad de componentes muy baja, y que está siendo actualmente empleada en sistemas de control industriales

ASIC implementation of an ARM - based system on chip

This paper presents the hardware architecture of a System on Chip (SoC) implemented in an ASIC. It has been designed for a wide range of applications and will be used in a power line modem. A set of reusable cells based on AMBA standard has been also designed, included memory, interrupt controller and peripherals. Presented architecture implements an ARM© processor, a 32-bit RISC processor which is becoming a RISC standard

Contribuciones a la automatización de diseños analógicos

La automatización del diseño analógico ha experimentado en los últimos años, un notable avance. La popularidad alcanzada por los circuitos ASICs, y la constatación de que la mayor parte de ellos contiene una importante circuitería analógica, son las caus

FASY: A fuzzy-logic based tool for analog synthesis

A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies