Hardware prototyping and validation of a W-ΔDOR digital signal processor

Microwave tracking, usually performed by on ground processing of the signals coming from a spacecraft, represents a crucial aspect in every deep-space mission. Various noise sources, including receiver noise, affect these signals, limiting the accuracy of the radiometric measurements obtained from the radio link. There are several methods used for spacecraft tracking, including the Delta-Differential One-Way Ranging (ΔDOR) technique. In the past years, European Space Agency (ESA) missions relied on a narrowband ΔDOR system for navigation in the cruise phase. To limit the adverse effect of nonlinearities in the receiving chain, an innovative wideband approach to ΔDOR measurements has recently been proposed. This work presents the hardware implementation of a new version of the ESA X/Ka Deep Space Transponder based on the new tracking technique named Wideband ΔDOR (W-ΔDOR). The architecture of the new transponder guarantees backward compatibility with narrowband ΔDOR

Radio link design for unmanned aerial vehicles (UAVS) WITH SQAM/TQAM configuration and alamouti/STBC codes

In this paper, we propose a new design of radio link for Unmanned Aerial Vehicles (UA Vs) with respect to the symbol error rate (SER), Alamouti coding and space time block code (STBC)of M-ary θ-quadrature amplitude modulation (QAM) i.e. Square-QAM (SQAM) and Triangular-QAM (TQAM) in presence of additive white Gaussian noise (AWGN) and channel fading in a MIMO radio link. Moreover we consider the error performance of the regular triangular/square quadrature amplitude modulation. In particular using an accurate exponential bound of complementary error function, we determine an approximation for the symbol error rate of T/S-QAM over AWGN in the fading channels. At the end some simulation results verify our theoretical results and we compare our work with other research

Reducing power dissipation in pipelined accumulators

Fast accumulation is required for units such as Direct Digital Frequency Syntehesis (DDFS) processors which, together with a digital to analog converter, generate periodic waveforms. In these units, waveforms with high frequency resolution are obtained if the clocking frequency of the digital processor is high (GHz range in today's technologies). Accumulators necessary for DDFS are then deeply pipelined down to the bit-level with two main consequences: high power dissipation, due to the large number of latches/flip-flops, and large latency dependent on the granularity of the applied pipelining. In this work, we address the two issues of reducing the power dissipation in the accumulator by applying selective clock gating, and reducing the accumulation latency by pipelining the adder to adapt the delay of the carry-chain to the necessary clock period. © 2008 IEEE

Residue number system for low-power DSP applications

In previous works ([1]-[8]) we performed different experiments implementing FIR filtering structures. Each filter was implemented using both the Two's Complement System (TCS) and the Residue Number System (RNS) number representations. The comparison of these two implementations allows to conclude that, for these applications, the RNS uses less power than the TCS counterpart. The aim of the present paper is to highlight the reasons of this power consumption reduction. © 2007 IEEE