VOVHDL: A verification-oriented dialect of VHDL

This paper focuses on the communication protocols used for system level modeling and on their VOVHDL implementation. Section 2 summarizes the model for communication we propose. Section 3 lists the restrictions and the extensions imposed on the standard language to yield VOVHDL. Section 4 draws some conclusions. 2. The communication model Protocols play a key role in the communication model and in the overall modelling strategy [CCPB93] and distinguish this approach from the pure use of VHDL or of Process Algebras, as it benefits from the advantages of both. Communications among processes and with the external world are performed through Communication Channel

System-Level Modeling and Verification: a Comprehensive Design Methodology

* Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level. 1. Introduction The boundaries of hardware description are rapidly migrating towards higher and higher levels of abstraction. Until not long ago, designers mainly worked at register-transfer level, whereas new activities at system-level are now emerging. Systems are conceived before partitioning between hardware and software realization takes place, so that many alternatives can be explored before defining the final hardware/software architecture. Among the most relevant activities at system-level, we list specification description and validation, and system description and verification. Most efforts in..

System-level fault modeling and test pattern generation with process algebras

The increasing complexity of systems is challenging designers with new issues, such as description, validation, verification, and testing at system level. This paper advocates the use of Process Algebras as a mathematically sound formalism to describe, to validate, to verify, and to generate test patterns at system level. Its main contribution is twofold: on one hand the definition of a general-purpose fault model of faulty communications between fault-free, concurrently evolving processes, on the other hand the implementation of an automatic test pattern generation procedure, as a variant of the weak bisimulation algorithm, normally used to prove the observational equivalence of processes. Two examples are provided to support the claim for validity: the functional fault model proposed by S. M. Thatte and J. A. Abraham for microprocessors is expressed in the new framework and some functional faults on a bus structure are modeled. Experimental results concerning the Process Algebra de..

An efficient tool for system-level verification of behaviors and temporal properties

In this paper the use of Process Algebras is advocated as a solution for system-level description of structure, communication and behavior, while an action-based Temporal Logic is used to specify and check system-level properties. It is shown how SEVERO, a tool for describing and verifying finite state systems, can be used to integrate in the unified framework of symbolic manipulations both descriptive and prescriptive aspects. Experimental results show the efficiency of the BDD-based implementation of the proof procedures

A methodology for system-level design for verifiability

Working at system level is attracting increasing interest. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports verification. Starting from a description in a proper subset of VHDL, a Petri Net description is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra manipulation supports formal equivalence proofs. Experimental results show that the approach is feasible also for real-size industrial case

A New Functional Fault Model for System-Level Descriptions

* Process Algebras are a suitable formalism both for system-level description and for ATPG with formal verification techniques. A functional fault model for System-Level descriptions is presented and experimental data are reported. The contributions of this paper are the definition of a general-purpose fault model for concurrently evolving processes and the implementation of a test pattern generation procedure, as a variant of the testing equivalence proof. A complete test system is implemented, allowing to describe systems, describe faults and generate test patterns whithin the same environment. 1. Introduction As technological advancements allow to integrate on a chip what in the near past was considered a complex system, hardware designers are confronted with systemlevel issues, rather than with the more familiar registertransfer or gate levels. Description, validation, synthesis, verification, and testing at system-level must respond to new demands, such as dealing with the sy..

The General Product Machine: a New Model for Symbolic FSM Traversal

FORMAL METHODS IN SYSTEM DESIGN, KLUWE