One-time-programmable memory in LTPS TFT technology with metal-induced lateral crystallization

A simple and reliable one-time-programmable (OTP) memory for low-temperature polysilicon thin-film-transistor technology with metal-induced lateral crystallization (MILC) is developed. The antifuse memory element is based on the breakdown of thin silicon dioxide deposited on smooth surface achieved by MILC. The effects of crystallization process and electrode configurations on the memory characteristics, including statistical variations, are studied. A read current margin of 10 6 is achieved for the fresh and programmed memory element. Functional OTP memory array with compact layout and high disturb immunity using a split supply configuration is also demonstrated. © 2006 IEEE

Integrated Nanosystems with Junctionless Crossed Nanowire Transistors

Junctionless field-effect transistors (FETs) are promising emerging devices with simple doping profiles. In these devices, the channel is uniformly doped without the need for extremely good lateral doping abruptness or high thermal budget at source/channel and drain/channel junctions. This implies that device customization requirements are simplified compared to conventional enhancement-mode FETs. However, junctionless FETs have been discussed exclusively in the context of MOSFET replacement assuming other CMOS manufacturing, circuit and interconnect paradigms to be preserved intact. In this paper we argue for integration of junctionless devices into emerging nanofabrics. We propose junctionless crossed-nanowire FETs (xnwFETs) as the active devices for the Nanoscale Application Specific Integrated Circuits (NASICs) crossed nanowire fabric. We show that in addition to reducing customization requirements for individual nanodevices, the simpler device doping profile enables a scalable manufacturing pathway for NASICs where alignment and overlay requirements are minimized. In this pathway, a uniform 2-D nanowire grid may be assembled using unconventional or self-assembly based approaches without any overlay constraints. Overlay requirements exist only for subsequent photolithography steps, which is expected to be very precise (3σ = ±3.3nm for 16nm technology node)