Electrodeposition of Ni-Si Schottky barriers

Electrodeposition is being used to fabricate magnetic microstructures directly on patterned n-type Si wafers of various substrate resistivities. The Ni-Si Schottky barrier is characterized and found to be of high quality for relatively low Si resistivities (1-2 Omega(.)cm), with extremely low reverse leakage. It is shown that a direct correlation exists among the electrodeposition potential, the roughness, and the coercivity of the films. A conductive seed layer or a back contact is not compulsory for electrodeposition on Si with resistivities up to 15 Omega(.)cm. This shows that electrodeposition of magnetic materials on Si might be a viable fabrication technique for magnetoresistance and spintronics applications

Low power hydrogen gas sensors using electrodeposited PdNi-Si Schottky diodes

The use of electrodeposited PdNi-Si Schottky barriers as low power Hydrogen sensors is investigated. The Palladium content of the film causes the Hydrogen molecules to dissociate and be absorbed by the film, changing the metal work function and Schottky barrier current. In this work we show that electrodeposited Pd(Ni)-Si Schottky barriers exhibit very low reverse bias currents compared to evaporated Schottky diodes. The Schottky diodes were fabricated on 0.5-1.5 ohmcm 100 n-type Si by electrodeposition of PdNi followed by evaporation of Aluminium contact pads. Electrical measurements at different Hydrogen pressures were performed on back to back Schottky diodes in a vacuum chamber using pure Nitrogen and a 5% Hydrogen-Nitrogen mixture. Very low currents of 1nA were measured in the absence of Hydrogen. Large increases in the currents, upto a factor of 100, were observed upon exposure to different Hydrogen partial pressures. A back to back configuration forms a device that draws extremely low power when idle. The low idle current, simplicity of the fabrication process and ability to easily integrate with conventional electronics proves the suitability of electrodeposited PdNi-Si Schottky barriers as low power Hydrogen sensors

Metal-catalyst-free growth of silica nanowires and carbon nanotubes using Ge nanostructures

The use of Ge nanostructures is investigated for the metal-catalyst-free growth of silica nanowires and carbon nanotubes (CNTs). Silica nanowires with diameters of 10-50 nm and lengths of ? 1 ?m were grown from SiGe islands, Ge dots, and Ge nanoparticles. High-resolution transmission electron microscopy (HRTEM) and energy dispersive X-ray spectroscopy (EDS) reveal that the nanowires grow from oxide nanoparticles on the sample surface. We propose that the growth mechanism is thermal diffusion of oxide through the GeO2 nanostructures. CNTs with diameters 0.6-2.5 nm and lengths of less than a few ?m were similarly grown by chemical vapor deposition from different types of Ge nanostructures. Raman measurements show the presence of radial breathing mode peaks and the absence of the disorder induced D-band, indicating single walled CNTs with a low defect density. HRTEM images reveal that the CNTs also grow from oxide nanoparticles, comprising a mixture of GeO2 and SiO2

Growth of Carbon Nanotubes on HfO2 towards Highly Sensitive Nano-Sensors

Carbon nanotube (CNT) growth on HfO2 is reported for the first time. The process uses a combination of Ge and Fe nanoparticles and achieves an increase in CNT density from 0.15 to 6.2 mm length/mm2 compared with Fe nanoparticles alone. The synthesized CNTs are assessed by the fabrication of back-gate CNT field-effect transistors with Al source/drain contacts for nano-sensor applications. The devices exhibit excellent p-type behavior with an Ion=Ioff ratio of 105 and a steep sub-threshold slope of 130 mV/dec

Asymmetric gate induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from ?50 to 200?C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain–body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical (110) pillar sidewalls and the horizontal (100) wafer surface

Depletion-Isolation Effect in Vertical MOSFETs During the Transition From Partial to Fully Depleted Operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm