Arbiters: an exercise in specifying and decomposing asynchronously communicating components

AbstractA method is presented for the formal specification and decomposition of asynchronously communicating components. The method is demonstrated by the design of some arbiters. An arbiter is a hardware primitive that realizes the mutual exclusive access of processes to their critical sections. It is shown how large arbiters can be decomposed into small ones, and how the communication behaviour of arbiters can be specified concisely and conveniently in a simple program notation. Furthermore, it is shown that the syntax of a program may guide the designer in the verification, and even derivation, of possible decompositions in a calculational style

Asynchronous Circuits

Digital VLSI circuits are usually classified into synchronous and asynchronous circuits. Synchronous circuits are generally controlled by global synchronization signals provided by a clock. Asynchronous circuits, on the other hand, do not use such global synchronization signals. Between these extremes there are various hybrids. Digital circuits in today's commercial products are almost exclusively synchronous. Despite this big difference in popularity, there are a number of reasons why asynchronous circuits are of interest. In this article, we present a brief overview of asynchronous circuits. First we address some of the motivations for designing asynchronous circuits. Then, we discuss different classes of asynchronous circuits and brie y explain some asynchronous design methodologies. Finally, we present a typical asynchronous design in detail

A Methodology for Correct-by-Construction Latency Insensitive Design

In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a functionally equivalent synchronous implementation that can tolerate arbitrary communication latency between latches. By using latches we can break a long wire in short segments which can be traversed while meeting a single clock cycle constraint. The overall goal is to obtain a design that is robust with respect to delays of long wires, in a shorter time by reducing the multiple iterations between logical and physical design, and with performance that is optimized with respect to the speed of the single components of the design. In this paper we describe the details of the proposed methodology as well as report on the latency insensitive design of PDLX , an out-of-order microprocessor with speculative-execution