Design and Implementation of IoT-based HVAC and Lighting System for Energy Saving

Building Energy Management System(BEMS) technology is under study as one of the various solutions to environmental problems such as depletion of energy resources, global warming, and climate change. Solving the energy problems of the future BEMS is not the only goal. Occupants must be guaranteed a comfortable environment. HVAC systems and lighting systems are a large part of building energy consumption, which also means that it is an important part of energy conservation. In this paper, we propose IoT-based HVAC and Lighting(I-HVAC&L) system for HVAC system and lighting system management. With I-HVAC&L System, you can save energy efficiency without compromising the convenience of residents’

Design and Implementation of IoT-based HVAC and Lighting System for Energy Saving

Building Energy Management System(BEMS) technology is under study as one of the various solutions to environmental problems such as depletion of energy resources, global warming, and climate change. Solving the energy problems of the future BEMS is not the only goal. Occupants must be guaranteed a comfortable environment. HVAC systems and lighting systems are a large part of building energy consumption, which also means that it is an important part of energy conservation. In this paper, we propose IoT-based HVAC and Lighting(I-HVAC&L) system for HVAC system and lighting system management. With I-HVAC&L System, you can save energy efficiency without compromising the convenience of residents’

Energy Storage System Control Algorithm by Operating Target Power to Improve Energy Sustainability of Smart Home

As energy issues are emerging around the world, a variety of smart home technologies aimed at realizing zero energy houses are being introduced. Energy storage system (ESS) for smart home energy independence is increasingly gaining interest. However, limitations exist in that most of them are controlled according to time schedules or used in conjunction with photovoltaic (PV) generation systems. In consideration of load usage patterns and PV generation of smart home, this study proposes an ESS control algorithm that uses constant energy of energy network while making maximum use of ESS. Constant energy means that the load consumes a certain amount of power under all conditions, which translates to low variability. The proposed algorithm makes a smart home a load of energy network with low uncertainty and complexity. The simulation results show that the optimal ESS operating target power not only makes the smart home use power constantly from the energy network, but also maximizes utilization of the ESS. In addition, since the smart home is a load that uses constant energy, it has the advantage of being able to operate an efficient energy network from the viewpoint of energy providers

An IoT-Based Home Energy Management System over Dynamic Home Area Networks

A smart grid (SG) has attracted great attention due to recent environmental problems. SG technologies enable users, such as energy system operators and consumers, to reduce energy consumption and the emission of greenhouse gases, by changing energy infrastructure more efficiently. As a part of the SG, home energy management system (HEMS) has become increasingly important, because energy consumption of a residential sector accounts for a significant amount of total energy consumption. However, a conventional HEMS has some architectural limitations on scalability, reusability, and interoperability. Furthermore, the cost of implementation of a HEMS is very expensive, which leads to the disturbance of the spread of a HEMS. Therefore, this paper proposes an Internet of Things- (IoT-) based HEMS with lightweight photovoltaic (PV) system over dynamic home area networks (DHANs), which enables the construction of a HEMS to be more scalable, reusable, and interoperable. We suggest the techniques for reducing the cost of the HEMS with various perspectives on system, network, and middleware architecture. We designed and implemented the proposed HEMS and conducted a experiment to verify the performance of the proposed system

A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer

This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA

Low-Noise Potentiostat Readout Circuit with a Chopper Fully Differential Difference Amplifier for Glucose Monitoring

This paper presents a low-noise potentiostat readout circuit with a chopper fully differential difference amplifier (FDDA) for glucose monitoring. Glucose monitoring is necessary for the early diagnosis of diabetes complications and for health management. Ammeter electrochemical sensors are widely used for glucose detection, and in general, a three-electrode structure of a reference electrode (RE), a counter electrode (CE), and a working electrode (WE) is implemented with a potentiostat structure. A low-noise characteristic of the readout circuit is essential for highly accurate glucose monitoring. The chopping technique can reduce low-frequency noises such as 1/f noise and can achieve the required low-noise characteristic. The proposed potentiostat readout circuit is based on a low-noise chopper FDDA with a class-AB output stage. The implementation of the chopper FDDA scheme of the potentiostat readout circuit can decrease the number of amplifiers in the control part of the potentiostat, with reduced power consumption and a wide dynamic output range. The negative feedback loop of the inverting amplifier scheme with the FDDA maintains the voltage between the WE and RE constants. The negative feedback loop tracks the reference voltage of the RE with an input voltage of the WE. The proposed potentiostat readout circuit is designed in the standard 0.18 µm CMOS process, and the simulated current consumption is 48.54 μA with a 1.8 V power supply. The simulated input-referred noise level was 8.53 pArms

Current-Feedback Instrumentation Amplifier Using Dual-Chopper Fill-In Technique

In this study, we describe a dual-chopper glitch-reduction current-feedback instrumentation amplifier (CFIA) with a ripple reduction loop. The amplifier employs the chopping technique to reduce low-frequency noise, such as 1/f noise. A glitch caused by chopping occurs at each chopper clock edge and results in intermodulation distortion (IMD). Owing to the input offset, the chopping technique also produces ripples. In this study, the glitch-induced IMD was reduced using a fill-in technique whereby only neat signals were alternately used as outputs by avoiding the glitch section with dual-chopping channel CFIA. To avoid using a high-order, low-frequency filter, a ripple reduction loop was implemented to reduce the ripple generated by chopping. The CFIA is based on a low-noise chopper fully differential difference amplifier with a cascode stage and a Monticelli-class AB output stage, which can drive a larger load and increase power efficiency. The proposed dual-chopper CFIA was fabricated using a 0.18 µm CMOS standard process, and its current consumption with a 1.8-V power supply is 29.5 μA. The proposed CFIA has a gain of 51 V/V, input referred noise of 53.3 nV/√Hz at 1 Hz, and a noise efficiency factor of 4.48