17 research outputs found

    From ProCoS to Space and Mental Models A Survey of Combining Formal and Semi-formal Methods

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    Operation Refinement for VDM-like Specifications

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    properties and applications to term rewriting systems. Journal of the ACM 27(4), 797--821 , October 1980. [41] G' erard Huet and Derek C. Oppen. Equations and rewrite rules: A survey. In R. V. Book, editor, Formal Languages: Perspectives and Open Problem, pages 349--405. Academic Press, 1980. [42] Cliff B. Jones. Systematic Software Development using VDM . Series in Computer Science. Prentice-Hall International, Second edition, 1990. [43] Cliff B. Jones, Kevin D. Jones, Peter A. Lindsay, and Richard Moore. mural - A Formal Development Support System. Springer-Verlag, 1991. [44] St' ephane Kaplan. Conditional rewrite rules. Theoretical Computer Science 33, 175--193, 1984. [45] St' ephane Kaplan. Simplifying conditional term rewriting systems. Technical Report CS 86-08, Weizmann Institute of Science, Rehovot, Israel , 1986. [46] Thomas K aufl. The program verifier Tatzelwurm. In Heinrich Kersten, editor, Sichere Software - Formale Spezifikation und Verifikation vertrauenswurdiger Systeme..

    Sichere Systeme

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    Lecture Engineering

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    Combining Methods for the Livelock Analysis of a Fault-Tolerant System

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    This article presents experiences gained from the verification of communication properties of a large-scale real-world embedded system by means of formal methods. This industrial verification project was performed for a fault-tolerant system designed and implemented by Daimler-Benz Aerospace for the International Space Station ISS and focused essentially on deadlock and livelock analysis. The approach is based on CSP specifications and the model-checking tool FDR. The tasks are split into manageable subtasks by applying abstraction techniques for restricting the specifications to the essential communication behavior, modularization according to the process structure, and a set of generic theories developed for the application

    Deadlock Analysis for a Fault-Tolerant System

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    . This article presents an approach for the verification of communication properties in large-scale real-world embedded systems by means of formal methods. It is illustrated by examples and results obtained during an industrial verification project performed for a faulttolerant system designed and implemented by Daimler-Benz Aerospace for the International Space Station ISS. The approach is based on CSP specifications and the model-checking tool FDR. The task is split into manageable subtasks by applying an abstraction technique for restricting the specifications to the essential communication behaviour, modularization according to the process structure, and a set of generic theories developed for the application. 1 Introduction One of the essential obstacles for the acceptance of formal methods during the last years is their failure to scale up to realistic applications. In our experience this problem can only be overcome by a combination of methods and the use of suitable tools that..
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