High performance memory architectures with dynamic locking cache for real-time systems

In modern computers, memory hierarchies play a paramount role in improving the average execution time. However, this fact is not so important in realtime systems, where the worst-case execution time is what matters the most. System designers must use complex analyses to guarantee that all tasks meet their deadlines. As an alternative to making those complex analyses, it is proposed to build a memory hierarchy such that it provides high performance coalesced with high predictability. At the same time, the memory assist should imply small-scale modifications in the hardware. The solution is to be centred on instruction fetching since it represents the highest number of memory accesses. 1

Departamento de Informática de Sistemas y Computadores

Abstract: The unpredictable behavior of conventional caches presents several problems when used in real-time multitask systems. It is difficult to know its effects in the Worst Case Execution Time and it introduces additional delays when different tasks compete for cache contents in multitask systems. This complexity in the analysis may be reduced using alternative architectures to cache memories, that improves predictability but obtaining similar performance. This is the case of locking caches, that may preload and lock cache contents, precluding the replacement during system operation, thus making cache and system behavior more predictable by means of simple, well-known and easy-to-use algorithms. This work presents an analysis of worst-case performance obtained with the static use of locking caches versus worst-case performance obtained with conventional (non-locking) caches. Analysis results show that predictability can be reached with no loss of performance, and the scenarios where the locking cache provides similar performance to conventional caches may be estimated from system parameters like task size, cache size, level of locality and level of interference, without running any experiment. Key-words: real-time systems, cache memories, locking cache, schedulability analysis, performance.

Using Genetic Algorithms in Content Selection for Locking-Caches

Modern processors include in their cache memories the ability to preload and lock a set of instructions, avoiding its replacement from cache. This ability may be useful in real-time, multitask systems, where response time of tasks must be a priori known. Locking cache contents makes the system predictable, simplifying the system analysis when calculating execution and response time of tasks. As cache memories improve system performance, real-time systems must take advantage of the speedup given by these memories. Selection of instructions to be loaded and locked in cache must be carefully accomplished to obtain the best performance in addition to predictability

Performance Comparison Of Locking Caches

Static use of locking caches is a useful solution to take advantage of cache memories in real-time systems. Locking cache operates preloading and locking a set of instructions, thus cache contents are a-priori known and remain unchanged during system operation. This solution eliminates the unpredictable behavior of conventional caches, making easy to accomplish the schedulability test through simple and well-known tools. Once attained predictability, in this paper we analyze the performance of this schema compared to conventional cache, as function of system size and cache size. We also study the influence of the scheduler (either fixed or dynamic priority). Copyright 2003 IFAC Keywords: real-time systems, cache memories, scheduling algorithms, performance analysis, genetic algorithms. 1