Elektrische Verbindungen in hochdichter Rasteranordnung

Electrically conducting connection between a first and a second boundary surface of a substrate (8) of an electronic switch with several leads (3) electrically insulated from each other is claimed. The novelty is that the leads (3) are arranged in a connecting element having first and second surfaces, so that both surfaces are connected, and the first surface partially coincides with the first boundary surface and the second surface partially coincides with the second boundary surface. Prodn. of the connection is also claimed. USE - For inserting a connecting element in substrate materials of microelectronics as vertical through contacts

Mikromedi. Teilvorhaben: Chip Scale Packages auf Einzelchips Abschlussbericht

SIGLEAvailable from TIB Hannover: F01B1622+a / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekVDI/VDE Technologiezentrum Informationstechnik GmbH, Berlin (Germany); Bundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman

Bump on flexible lead for wafer level packaging

A chip-to-substrate interconnect technology is introduced which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. Increased flexibility, i e. purely elastic response, of the bumps can lead to an increase in the reliability of large Flip Chips. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper line embedded in a polymer-bridge which is located over an air gap. For a small bump height, which is necessary to achieve a small package height, the stress due to CTE mismatch is then accommodated within the flexible lead. FEM simulations were performed and prototype chips have been designed and fabricated using wafer level packaging processing methods, such as photolithography, electroplating and wet-etching. The process flow and assembly of the flexible interconnects without underfill are presented and discussed

JESSI-basic and long term research packaging BT 4

Vertical integrating systems of high complexity with shortest chip to chip interconnects require numerous electrical feedthroughs in the MCM-substrate and vertical interconnects between mating submodules. A planar integrating hybrid technique was employed to achieve a stackable MCM-type. This chip-first concept deliveres flat planar multichip modules. Embedded components are directly interconnected by a thinfilm multilayer wiring. Polymer dielectrics and conductor layers are deposited by thinfilm processing. The separately pretested submodules with a both sided bump-array metallization are stacked to realize shortest interconnects between a large number of ICs. To accomplish repair or system changes removable elastomeric connectors are sandwiched between mating substrates and kept under moderate pressure. Compared to common 2D-integration reduced signal delay and reduced parasitc effects like resistance, capacitance, crosstalk and inductance result in better electrical properties. Small pretestable subunits with a moderate number of integrated components and their easy exchange in the stack should lead to a high system yield. A test chip for the measurement of package-induced stress had to be developed. Design concepts have been evaluated and teststructures were simulated. The characteristic of the teststructures on the fabricated wafers were measured and the calibration was done. The thermally-induced mechanical stress was determined in static and transient simulations that were confirmed in the measurements. In order to test the system in a more realistic application, chips were then assembled onto various substrates by both adhesive and flip-chip bonding with underfiller. The set up was able to detect the residual stresses in these configurations. (orig.)SIGLEAvailable from TIB Hannover: F97B820 / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekBundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman

Polymer based thin film coils as a power module of wireless neural interfaces

For the conventional Utah Electrode Array (UEA) to be able to function without transcutaneous wire connections, a kind of power source is needed in an integrated form with the UEA. To develop such wireless neural interfaces, inductive coupling between two coils was used to deliver power to the integrated electronics. The power receiver coil was microfabricated as a polymer based component, and its electrical characteristics and performance in power transmission were investigated in dry condition

Entwicklung photoinduzierter Prozesse fuer die Aufbau- und Verbindungstechnik Teilprojekt: Entwicklung von Technologien fuer die Systemintegration auf der Basis photoinduzierter Prozesse und Einbettechniken. Abschlussbericht

In all forms of multi-chip-modules (MCMs) developed so far, the interconnects between ICs and substrate metallization are achieved by wire bonding, tape automated bonding or flip chip bonding techniques. The resulting system reliability reduces depending to a large extend upon the integrity of each of the interconnecting solder joints in the system. Also interconnection density and speed of operation are affected by the presence of bonds. To achieve near monolithic character in a MCM-version a planar integrating hybrid technique was investigated. In this approach individual ICs are inserted into premanufactured window openings of ceramic substrates and fixed in their position by epoxy application around their perimeter. A thin film multilayer can be realized on the planar topside of this multichip embedding substrate. Usual thin film techniques are applied for deposition and patterning of polymer dielectrics and metallization levels. The thin film metallization, electroplated on a sputtered base, does all the interconnects from chip to substrate and from chip to chip as well in one process step without any bond or solder joint. The method of direct interconnection closely resembles a monolithic integration and clearly distinguishes from the bonding techniques. Compared to bonding a higher level of integration, higher reliability and better electrical characteristics can be achieved. A planar multichip technique without parasitic discontinuities in metal interconnects and with a controlled signal impedance in the polymer dielectric allows high speed applications. Flat embedding modules with narrow placed chips occupy minimal board area at reduced volume and weight. Commercial ICs of different technology can be integrated without special requirements concerning size, thickness, or pad-pattern. Embedding can even be extended to capacitive components, optical-, electrical- and thermal feed through elements. As proof of concept a demonstrator modul with 2 layers of Au-wiring in a Polyimide multilayer was fabricated on top of a ceramic substrate with 4 embedded Si-testchips. The key processes developed include several photo induced methods for structuring substrate material, dielectric layers and metal interconnects. (orig)In den bisher entwickelten Multi-Chip-Modulen (MCMs) sind die Verbindungen zwischen den ICs und der Substrat/Metallisierung durch Draht-Bond, TAB-Technik, oder Flip-Chip-Lottechnik vollzogen worden. Folglich haengt die Zuverlaessigkeit des Systems in grossem Masse von der Integritaet jeder einzelnen Bondverbindung ab. Ebenso werden die Verdrahtungsdichte und die Signalverarbeitung von den zahlreichen Bondverbindungen eingeschraenkt. Im FuE-Vorhaben ist eine planar integrierende Duennfilm Hybrid Technik zum Bau von MCMs untersucht worden. Eine Epoxy-Fuegetechnik zur Oberflaechen-buendigen Einbettung von individuellen ICs in Laser-strukturierte Oeffnungen von keramischen Substraten schafft die notwendig planare Voraussetzungen zur Anlage einer Mehrlagen-Verdrahtung. Die direkte Ankontaktierung eingebetteter ICs an eine einheitliche Duennfilm-Metallisierung durch Sputter- und Galvanik-Prozesse vermeidet jegliche Bondstelle. Die Direktkontaktierung unterscheidet sich deutlich von den ueblichen Bond-Techniken. Im Vergleich sind ein hoeherer Integrationsgrad, hoehere Zuverlaessigkeit und bessere elektrische Charakteristiken moeglich. Die entwickelte hybride Aufbautechnik kommt einer monolithischen Integration am naechsten. Ohne Unstetigkeiten bei der IC-Kontaktierung und mit einer Impedanz-kontrollierten Fuehrung der Signalleitungen im Polyimid-Dielektrikum koennen Anwendungen im HF-Bereich erschlossen werden. Bei dichter IC-Belegung haben flache Einbettungsmodule mit reduziertem Volumen und Gewicht einen minimalen Platzbedarf. Dabei ist die Einbettechnik nicht nur auf beliebige ICs unterschiedlicher Technologie beschraenkt, sondern die Einbettung kapazitiver Bauteile, optischer-, elektrischer-, thermischer Durchfuehrungen ist ebenso moeglich. Technologie-demonstrator-MCMs mit einer 2-lagigen Au-Metallisierung im Polyimid-Multilayer wurden auf keramischen Substraten mit 4 planar eingebetteten Si-Testchips hergestellt. Die entwickelten Herstellungsprozesse beinhalten photoinduzierte Methoden zur Strukturierung von Substraten, dielektrischen Schichten und metallischen Verbindungen. (orig.)Available from TIB Hannover: F94B0781 / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEBundesministerium fuer Forschung und Technologie (BMFT), Bonn (Germany)DEGerman