A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies

The paper presents a generalization of the Groszkowski’s result in differential oscillators, providing novel equations to describe the oscillation frequency dependence on the harmonic content. The effect of the common-mode oscillation is rigorously included. Moreover, an additional term, arising from the dependence of the transistor current on the drain voltage, which is dominant any time ohmic operation occurs, is disclosed here for the first time. This framework is applied to Van der Pol oscillators, both nMOS and CMOS, designed in a 28-nm bulk CMOS technology. The results correctly match the oscillation frequency dependence derived from detailed circuit simulations. The analysis shows that, when even harmonics are relevant, the classical Groszkowski’s result is not able to account for close-in phase noise performance. The novel theoretical framework fully justifies, instead, the simulation results and sheds new light on the flicker noise up-conversion mechanisms in the considered oscillator structures

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

An LO phase-shifting system based on digi- tal fractional-N bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to- time converter (DTC) nonlinearities. Synchronization between fractional-N PLL cores is achieved by clocking with the same reference clock the 16 modulator driving the frequency divider of each core. The adoption of a digital phase-offset correction technique canceling out timing skews greatly simplifies the reference-clock distribution and DTC matching. A dual-core prototype is implemented in a standard 28-nm CMOS process, where each element occupies 0.23-mm2 area and dissipates 20-mW power. An arbitrary phase shift between the LO outputs can be set over the 360◦ range with a resolution of 0.7 millidegree (19 bits). The rms phase accuracy is 0.76°, and the peak-to- peak phase error is 2.1°, without requiring any linearity or gain calibration. Each LO element features a −58.7 dBc in-band fractional spur and a −70 dBc reference spur, with a jitter versus power figure-of-merit of −253.5 and −250.0 dB for integer-N and fractional-N channels, respectively. The combined outputs of the two PLL cores reach an absolute jitter integrated from 1 kHz to 100 MHz (including spurs) of 38.2 and 59.78 fs, in integer-N and near-integer fractional-N operations, respectively

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the communication industry to set extremely challenging requirements on the integrated jitter of local oscillators [1]. In fractional-N PLLs, the adoption of a digital-to-time-converter (DTC) has become ubiquitous to meet performance targets, as it greatly improves integrated jitter by re-aligning the edges of the reference and the divider signals (top-left of Fig. 4.5.1) [2], [2]. Unfortunately, any DTC non-linearity converts the quantization error (QE) , driving the DTC into fractional spurs in the PLL spectrum, thus degrading the integrated jitter. Several digital techniques have been proposed to reduce the DTC non-linearity either at the cost of increasing hardware resources [3] or requiring calibration loops with long convergence times [4]. Other techniques dither the DTC control word [5], [6], spreading the spurious-tones power over a larger bandwidth, but the total jitter improvement is limited. This work introduces a fractional-spur-cancellation technique based on a multi-DTC topology with phase-shifted quantization-error sequences that allows the cancellation of the dominant fractional-spur tones and, at the same time, the reduction of the in-band phase-noise (PN). The concept is demonstrated in a 9.25GHz fractional-N DPLL, which achieves a total rms jitter of 77.1fs (including fractional spurs) for near-integer channels and an in-band fractional spur of −60.3dBc

4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Ultra-low-jitter and high-spectral-purity frequency synthesizers are key building blocks for high-performance wireless transceivers and $\text{FMCW}$ radars. A bang-bang $\text{PLL} (\text{BBPLL}$ ) is an attractive solution thanks to its small footprint and low power consumption; however, its operation in the $\text{fractional-N}$ mode is hindered by the large quantization error $(\text{Q-error})$ I caused by the non-integer frequency multiplication saturating the narrow input range of the bang-bang phase detector $(\text{BBPD})$ . A digital-to-time converter $(\text{DTC})$ is typically used to cancel the $\text{Q-error}$ in time domain [1] (Fig. 4.3.1 top-left). Unfortunately, the $\text{DTC}$ non-linearity can generate significant fractional spurs, thus corrupting the $\text{PLL}$ spectral purity and integrated jitter. Solutions to this problem rely on either improving the $\text{DTC}$ linearity or adopting a suitable randomization of the $\text{Q-error}$ sequence to generate lower spurs in the presence of the $\text{DTC}$ non-linearity. The constant slope $\text{DTC} (\text{CS-DTC})$ achieves superior linearity among $\text{DTC}$ architectures [2], even if further improvements are limited by the voltage sensitivity of current generators $(\text{CGs})$ and parasitic capacitances as well as by the non-linearity of the digital-to-analog converter $(\text{DAC})$ adopted in the circuit. On the other hand, those randomization techniques to reduce spurs typically require a larger $\text{Q-error}$ range [3], [4] that increases $\text{PLL jitter}$ for two reasons: the higher quantization-noise power and the larger random jitter induced by the wider range needed for the $\text{DTC}$ . This work introduces a $9.25-\text{to}-10.5\text{GHz} \text{fractional-N BBPLL}$ achieving $-71.9\text{dBc}$ fractional spur and a total rms jitter (including spurs) of $76.7\text{fs}$ at near-integer channels leveraging: $(\mathrm{i})$ a $\text{DTC}$ architecture (denoted as $inverse constant-slope DTC)$ I overcoming the $\text{CS-DTC}$ limitations and $(\text{ii})$ a $\text{Q-error}$ randomization technique (denoted as $FCW$ subtractive dithering), which keeps the $\mathrm{Q}- \text{error}$ range constant thus not degrading $\text{PLL jitter}

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

This work presents a fast-locking and low-jitter fractional- N bang-bang phase-locked loop (BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs, two novel techniques are introduced. A gear-shift technique, denoted as type-II gear-shift, avoids limit cycles in the phase-locked loop (PLL) frequency transient and optimizes the locking time of the main PLL loop. The adaptive frequency switching (AFS) technique reduces the PLL frequency error upon channel switching exploiting the already existing hardware. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.23 mm 2 and achieves a locking time always below 1.56 μ s (within 80 ppm accuracy) for frequency jumps up to 1.5 GHz over the 8.5–10 GHz tuning range. The measured rms jitter (integrated from 1 kHz to 100 MHz) is 48.6 fs for integer- N channels and 68.6 fs for near-integer fractional- N channels, with a worst case fractional spur of − 58.2 dBc. The power consumption is 20 mW, leading to a jitter-power figure of merit of − 253.2 and − 250.3 dB for integer- N and fractional- N channels, respectively

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter

The advent of the next-generation wireless communication standards demands increasingly faster transceivers, posing extremely challenging requirements on the frequency-synthesizer integrated jitter [1, 2]. As demonstrated in [1], the bang-bang digital-PLL (DPLL) architecture can meet the required jitter performance while synthesizing fractional-N frequencies, and it is highly attractive for its reduced power consumption, compact footprint, and straightforward integration in modern scaled CMOS technologies. However, due to the intrinsic bang-bang phase-detector (BBPD) quantization noise, analog PLLs still achieve superior performance in terms of the jitter-power product [2]. To overcome the BBPD quantization noise in DPLLs, [3] relies on an 8b ADC to digitize the PLL phase error with a physical resolution below the input-jitter, leading to increased design complexity, with an area and power penalty. The first attempt to reduce the quantization noise of a 1b TDC was done in [4] by implementing a charge-pump-based \Delta\Sigma TDC in a fractional-N DPLL. Unfortunately, the large delay introduced in the delta modulation path has so far hindered its adoption in low-jitter DPLLs. This work presents a 13GHz fractional-N DPLL achieving 79. 5fs random jitter and 107.6fs jitter including spurs in near-integer channels. The DPLL is based on a BBPD with (i) quantization noise shaping with a fine and tunable delta modulation, and (ii) a digital background adaptive-shaping-control technique to optimally reduce the BBPD quantization

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays

Achieving long-distance, high data-rate wireless connections at the 5G millimeter-wave (mm-wave) frequency bands requires ultra-low-jitter local oscillators (LOs) [1]-[3] and phased-arrays with very accurate beam-steering capability [4], [5]. In regard to jitter, digital bang-bang phase-locked loops (BBPLLs) have been recently shown as capable of satisfying the very stringent requirements, while at the same time occupying less area than their analog counterparts [3]. This makes them particularly well-suited to the so-called localized LO-generation approach, where a synthesizer is placed in each of the individual transceiver elements, to avoid routing of a global high-frequency signal across large ICs and to leverage the jitter suppression resulting from an equivalent over-the-air combination of the outputs [1]. To achieve accurate beam-steering with LO phase-shifting, highly linear mm-wave phase-shifters are then conventionally placed on each of the LO signals [4], [5], leading, unfortunately, to a substantial power, noise, and area overhead

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

This work introduces a bang-bang fractional-N phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.21 mm² and achieves an rms jitter (integrated from 1 kHz to 100 MHz) of 69.5 fs for integer-N synthesized channels, 79.7 fs for typical fractional-N channels, and 99.6 fs for near-integer fractional channels with a worst case fractional spur of -51.1 dBc. The power consumption is 10.8 mW, leading to a jitter-power figure of merit of -252.8 dB and -251.6 dB for integer-N and fractional-N channels, respectively