Ultralow-power adiabatic circuit semi-custom design

This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-mum CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to,a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3 divided by 6) even when the losses in power-clock generation are considered

A comparison of some circuit schemes for semi-reversible adiabatic logic

Four flip-flop-like adiabatic logic circuits, suited for a standard cell library implementation, were compared in terms of absolute energy consumption and effectiveness of adiabatic energy recovery. The energy performance of ECRL, IECRL, PAL and PFAL logic circuits was determined, by means of SPICE simulation, as a function of capacitive load and operational frequency. The comparison showed that the PFAL circuit is the best flip-flop-based adiabatic solution as far as power consumption is concerned

Simple model for positive-feedback adiabatic logic power consumption estimation

A model based on constant R-C elements for the calculation of the energy dissipated in adiabatic circuits with positive feedback is presented. The model can be used to estimate the energy dissipated as a Function of both the load capacitance and operating frequency with an error of < 8 and 18%, respectively