Strahlungstolerante digitale Taktgeneratorschaltungen für Anwendungen in der Hochenergiephysik

The main focus of the presented research is the development and experimental study of radiation-tolerant clock generation circuits intended for applications in high energy physics (HEP). Clock synthesis and the synchronization of systems on the scale of large experimental detectors is an important aspect of their successful implementation and a necessity for achieving their anticipated performance. Developments in this area to increase radiation tolerance and performance are motivated by emerging requirements for clock generation and distribution. The thesis reviews the requirements of existing and emerging systems with regards to radiation-tolerant clock generation. To characterize clock generation circuits and adequately assess their conformity with the identified requirements in radiation tests, a number of methods and instrumentation setups are developed and characterized. The presented approaches combine aspects of digital programmable logic, analog circuit design and and digital signal processing concepts. To address design challenges in deep submicron CMOS nodes, the design of radiation-tolerant all-digital PLL and CDR circuits is explored in this thesis. These circuits promise opportunities to improve the radiation tolerance of clock generators, and hence this thesis devises the design of a radiation-tolerant ADPLL/CDR circuit compatible with requirements of high energy physics (HEP) electronics. Using radiation testing, the sensitivity of the circuits is studied and mitigation strategies for identified limitations are discussed. Three such ADPLL/CDR circuits are developed and tested in the form of macro blocks targeting applications in frontend ASICs for high energy physics. The circuits demonstrate jitter performance, power efficiency and radiation tolerance comparable to or better than currently used conventional PLL circuits. As a final aspect, the improved testing instrumentation and methodology developed within this thesis is applied to uncover a previously unrecognized radiation sensitivity in a conventional, radiation-hardened clock generator circuit. An integrated planar on-chip inductor is experimentally identified as responsible for this sensitivity. Irradiation tests are performed to study and characterize the nature of this sensitivity. The results suggest that energy deposition, likely within dielectric materials surrounding the inductor wiring, alters the inductor's terminal impedance. This stimulates frequency errors with long recovery times in the oscillator. The manifestation of this effect in HEP radiation environments is studied using proton irradiation, where a mitigation strategy is experimentally validated. A reduction of the impact of this sensitivity is demonstrated. To help conclusively identifying the underlying mechanism responsible for the sensitivity within the inductor itself, further research opportunities are suggested.Die vorgelegte Dissertation befasst sich mit der Entwicklung und der experimentellen Untersuchung strahlungstoleranter und hochzuverlässiger Takterzeugungsschaltungen für Anwendungen in der Hochenergiephysik. Die Sychronisation von Komponenten und Systemen im Maßstab großer Detektorexperimente mithilfe solcher Schaltungen ist von zentraler Bedeutung für deren erfolgreiche Implementierung und das Erreichen der spezifizierten Leistungsparameter. Die Konzeption von aktuellen sowie zukünftigen Detektorgenerationen erfordern das Erreichen von zunehmend strikteren Anforderungen an Takterzeugung und -verteilung. Im ersten Teil der Arbeit werden drei komplementäre Methoden und Instrumentationskonzepte für Charakterisierungs- und Qualifikationsaufgaben solcher Schaltungen vorgestellt, um die Einhaltung der durch die Anwendung gegebenen Anforderungen in Strahlungstests zu uberprüfen. Die dazu verfolgten Ansätze kombinieren Aspekte aus den Bereichen flexibel programmierbarer Logikschaltungen, analoger Schaltungsentwicklung und digitaler Signalverarbeitung. Eine der größten Herausforderungen für analoge integrierte Schaltungen in hochintegrierten CMOS-Prozesstechnologien stellt deren aggressive Reduzierung der Versorgungsspannung dar. Als Ansatz zur Bewältigung dieser und weiterer Herausforderungen beschäftigt sich diese Arbeit als zweiten Schwerpunkt mit der Entwicklung von strahlungstoleranten, vollständig digital implementierten Phasenregelschleifen (engl. all-digital PLL) für Anwendungen in Beschleunigerexperimenten. Die digitale Umsetzung traditionell mit analogen Schaltungen implementierter Funktionalität ermöglicht das Verfolgen von neuen, vielversprechenden Ansätzen zur Strahlungshärtung von Takterzeugungsschaltungen. Als letzten Aspekt beschäftigt sich die Arbeit mit einer neuartigen Klasse von transienten Strahlungseffekten in Takterzeugungsschaltungen. Der erstmalige Nachweis sowie das Erkennen der praktischen Relevanz dieses Strahlungseffektes für Systeme mit hohen Genauigkeitsanforderungen wurde dabei erst durch die im ersten Teil der Arbeit durchgeführte Entwicklung verbesserter Messverfahren ermöglicht. On-Chip-Induktivitäten wurden hierbei als strahlungsempfindliche Schaltungskomponente innerhalb eines LC-Oszillators identifiziert. Mithilfe von Experimenten an Laser- und Schwerionenbeschleunigeranlagen wurden Untersuchungen zur Charakterisierung dieses Strahlungseffektes durchgeführt. Mithilfe dieser konnte gezeigt werden, dass die Deposition von Energie innerhalb der empfindlichen Komponente zu einer temporären Änderung ihrer Impedanz führt, was die Schwingfrequenz des untersuchten Oszillators messbar beeinflusst. Abschließend werden zu diesem Themenschwerpunkt weitere zu untersuchende Aspekte herausgearbeitet, mithile derer eine vollständige Erklärung des beobachteten Strahlungseffektes und der ihm zu Grunde liegenden Mechanismen im Bereich der Halbleiterphysik angestrebt wird

Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS

This article describes a previously unreported single-event radiation effect in spiral inductors manufactured in a commercial CMOS technology when subjected to ionizing radiation. Inductors play a major role as the component determining the frequency of LC tank oscillators, which is why any radiation effect in these passive components can have a detrimental impact on the performance of clock generation circuits. Different experiments performed to localize and characterize the singleevent effect (SEE) response in a radiation-hardened PLL circuit are discussed and presented together with a hypothesis for the underlying physical mechanism

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS

A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path, which stabilizes the CDR by compensating for an additional pole introduced in the VCO in order to harden it against ionizing particles. The CDR has a data rate of 2.56 Gb/s and uses In-Phase/Quadrature (IQ) clocks in combination with a frequency detector (FD) to increase the pull-in range. The circuit was designed in a 65 nm CMOS technology and has a core power consumption of only 34 mW. The circuit was tested while subjected to heavy-ions with a Linear Energy Transfer (LET) up to 62.5 MeV cm-2mg-1. Additionally, the circuit was irradiated using X-rays up to a Total Ionizing Dose (TID) of 350 Mrad

A High-resolution, Wide-range, Radiation-hard Clock Phase-shifter in a 65 nm CMOS Technology

The design and characterization results of a high-resolution phase-shifter are presented. The phase-shifter is designed with radiation hardening techniques and fabricated in 65 nm CMOS technology. The phase-shifter circuit can produce several output frequencies (40, 80, 160, 320, 640 or 1280 MHz) with an adjustable phase (48.4 ps resolution). It has been fully characterized displaying INL<0.61 LSB and DNL<0.44 LSB with the power consumption, depending on the output frequency, staying below 8 μW/MHz

The lpGBT PLL and CDR Architecture, Performance and SEE Robustness

We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. This CDR employs a novel loop architecture with a high-speed feed forward loop stabilization technique. A test circuit was fabricated in a 65 nm CMOS technology and has been tested experimentally for correct operation in the foreseen radiation environment

Extension of the R&D Programme on Technologies for Future Experiments

we have conceived an extension of the R&D programme covering the period 2024 to 2028, i.e. again a 5-year period, however with 2024 as overlap year. This step was encouraged by the success of the current programme but also by the Europe-wide efforts to launch new Detector R&D collaborations in the framework of the ECFA Detector R&D Roadmap. We propose to continue our R&D programme with the main activities in essentially the same areas. All activities are fully aligned with the ECFA Roadmap and in most cases will be carried out under the umbrella of one of the new DRD collaborations. The program is a mix of natural continuations of the current activities and a couple of very innovative new developments, such as a radiation hard embedded FPGA implemented in an ASIC based on System-on-Chip technology. A special and urgent topic is the fabrication of Al-reinforced super-conducting cables. Such cables are a core ingredient of any new superconducting magnet such as BabyIAXO, PANDA, EIC, ALICE-3 etc. Production volumes are small and demands come in irregular intervals. Industry (world-wide) is no longer able and willing to fabricate such cables. The most effective approach (technically and financially) may be to re-invent the process at CERN, together with interested partners, and offer this service to the community