A new approach to the analysis of electromagnetic FEM simulations results at electric field singularities

A new methodology to the analysis of the results of Finite-Element Modeling (FEM) simulations at electric field singularities is proposed. The method, that can be easily applied in the post-processing phase of the electromagnetic FEM analysis workflow, is based on the weighted averaging of the calculated electric field magnitude within small volumes including the singularity point under investigation. In the paper, the proposed approach is applied to the electrical stress analysis of a high-voltage device modeled by means of a commercial electromagnetic FEM tool. In comparison to the conventional metric of the maximum field evaluation usually adopted for the analysis of electrical stress in insulators, our approach features several advantages: (i) the outcome of the analysis is independent of the numerical grid refinement at the singularity, thus allowing direct comparison of calculated electric field with the material dielectric strength; (ii) the method is robust against slight modifications of the geometrical shape of the singularity; (iii) on the other hand, for a given shape, the analysis outcome responds to significant variations of the singularity size or, in other words, of its sharpness; (iv) in the analysis of high-voltage devices, the approach can be applied for the estimation of the discharge volumes corresponding to different singularity types of different device geometries. In the paper, the new methodology is explained in details and is applied to simple but significant case studies

Metallized ceramic substrate with mesa structure for voltage ramp-up of power modules

International audienceAs the available wide bandgap semiconductors continuingly increase their operating voltages, the electrical insulation used in their packaging is increasingly constrained. More precisely the ceramic substrate, used in demanding applications, represents a key multi-functional element is being in charge of the mechanical support of the metallic track that interconnects the semiconductor chips with the rest of the power system, as well as of electrical insulation and of thermal conduction. In this complex assembly, the electric field enhancement at the triple junction between the ceramic, the metallic track borders and the insulating environment is usually a critical point. When the electrical field at the triple point exceeds the critical value allowed by the insulation system, this hampers the device performance and limits the voltage rating for future systems. The solution proposed here is based on the shape modification of the ceramic substrate by creating a mesa structure (plateau) that holds the metallic tracks in the assembly. A numerical simulation approach is used to optimize the structure. After the elaboration of the structures by ultrasonic machining we observed a significant increase (30%) in the partial discharge detection voltages, at 10 pC sensitivity, in a substrate with a mesa structure when comparing to a conventional metallized ceramic substrate

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for Field-Programmable Gate Arrays (FPGAs) using eNVMs. We propose an eNVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switchbox arrangement. We show that these blocks yield an improvement in area and write time of up to 3x and 33x respectively vs. a regular Flash implementation. By integrating the designed blocks in a FPGA, we demonstrate an area and delay reduction of up to 28% and 34% respectively on a set of benchmark circuits. These reductions are due to the eNVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO2/Pt stack, while the lowest leakage power is achieved by InGeTe stack

Characterization and modeling of phase-change memories

Within this Ph.D. thesis work new topics in the field of Non-Volatile Memories technologies have been investigated, with special emphasis on the study of novel materials to be integrated in Phase-Change Memory (PCM) devices, namely:(a) Investigation of new phase-change materialsWe have fabricated PCM devices integrating a novel chalcogenide material: Carbon-doped GeTe (or simply, GeTeC). We have shown that C doping leads to very good data retention performances: PCM cells integrating GeTeC10% can guarantee a 10 years fail temperature of about 127°C, compared to the 85°C of GST. Furthermore, C doping reduces also fail time dispersion. Then our analysis has pointed out the reduction of both RESET current and power for increasing carbon content. In particular, GeTeC10% PCM devices yield about a 30% of RESET current reduction in comparison to GST and GeTe ones, corresponding to about 50% of RESET energy decrease.Then, resistance window and programming time of GeTeC devices are comparable to those of GST.(b) Advanced electrical characterization techniquesWe have implemented, characterized and modeled a measurement setup for low-frequency noise characterization on two-terminal semiconductor devices.(c) Modeling for comprehension of physical phenomenaWe have studied the impact of Self-induced Joule-Heating (SJH) effect on the I-V characteristics of fcc polycrystalline-GST-based PCM cells in the memory readout region. The investigation has been carried out by means of electrical characterization and electro-thermal simulations.La thèse de Giovanni BETTI BENEVENTI portes sur la caractérisation électrique et la modélisationphysique de dispositifs de mémoire non-volatile à changement de phase. Cette thèse a été effectuée dans le cadre d’une cotutelle avec l’Università degli Studi di Modena e Reggio Emilia (Italie).Le manuscrit en anglais comporte quatre chapitres précédés d’une introduction et terminés par uneconclusion générale.Le premier chapitre présent un résumé concernant l’état de l’art des mémoires a changement de phase. Le deuxième chapitre est consacré aux résultats de caractérisation matériau et électrique obtenus sur déposition blanket et dispositifs de mémoire à changement de phase (PCM) basées sur le nouveau matériau GeTe dopé carbone (GeTeC).Le chapitre trois s’intéresse à l’implémentation et à la caractérisation expérimentale d’un setup demesure de bruit a basse fréquence sur dispositifs électroniques a deux terminaux développé auxlaboratoires de l’Università degli Studi di Modena e Reggio Emilia en Italie.Enfin, dans le dernier chapitre est présentée une analyse rigoureuse de l’effet d’auto-chauffage Joulesur la caractéristique I-V des mémoires a changement de phase intégrant le matériau dans la phase polycristalline

Characterization and modeling of phase-change memories

La thèse de Giovanni BETTI BENEVENTI portes sur la caractérisation électrique et la modélisationphysique de dispositifs de mémoire non-volatile à changement de phase. Cette thèse a été effectuée dans le cadre d une cotutelle avec l Università degli Studi di Modena e Reggio Emilia (Italie).Le manuscrit en anglais comporte quatre chapitres précédés d une introduction et terminés par uneconclusion générale.Le premier chapitre présent un résumé concernant l état de l art des mémoires a changement de phase. Le deuxième chapitre est consacré aux résultats de caractérisation matériau et électrique obtenus sur déposition blanket et dispositifs de mémoire à changement de phase (PCM) basées sur le nouveau matériau GeTe dopé carbone (GeTeC).Le chapitre trois s intéresse à l implémentation et à la caractérisation expérimentale d un setup demesure de bruit a basse fréquence sur dispositifs électroniques a deux terminaux développé auxlaboratoires de l Università degli Studi di Modena e Reggio Emilia en Italie.Enfin, dans le dernier chapitre est présentée une analyse rigoureuse de l effet d auto-chauffage Joulesur la caractéristique I-V des mémoires a changement de phase intégrant le matériau dans la phase polycristalline.Within this Ph.D. thesis work new topics in the field of Non-Volatile Memories technologies have been investigated, with special emphasis on the study of novel materials to be integrated in Phase-Change Memory (PCM) devices, namely:(a) Investigation of new phase-change materialsWe have fabricated PCM devices integrating a novel chalcogenide material: Carbon-doped GeTe (or simply, GeTeC). We have shown that C doping leads to very good data retention performances: PCM cells integrating GeTeC10% can guarantee a 10 years fail temperature of about 127C, compared to the 85C of GST. Furthermore, C doping reduces also fail time dispersion. Then our analysis has pointed out the reduction of both RESET current and power for increasing carbon content. In particular, GeTeC10% PCM devices yield about a 30% of RESET current reduction in comparison to GST and GeTe ones, corresponding to about 50% of RESET energy decrease.Then, resistance window and programming time of GeTeC devices are comparable to those of GST.(b) Advanced electrical characterization techniquesWe have implemented, characterized and modeled a measurement setup for low-frequency noise characterization on two-terminal semiconductor devices.(c) Modeling for comprehension of physical phenomenaWe have studied the impact of Self-induced Joule-Heating (SJH) effect on the I-V characteristics of fcc polycrystalline-GST-based PCM cells in the memory readout region. The investigation has been carried out by means of electrical characterization and electro-thermal simulations.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

On the limitations of transipedance amplifiers as tools for low-frequency noise characterization

An experimental set-up for the characterization of low-frequency noise on two terminal devices is reported. The experimental set-up is based on the use of the commercial transimpedance amplifier (TA) EG&G5182. This paper addresses the influence of the TA on the noise characterization process by describing the TA as a non-ideal operational amplifier with a feedback resistor. The impact of the TA finite input resistance and voltage gain is highlighted through comparison with measurements carried out on resistors and diodes

Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current

A novel approach to optimize tunnel field effect transistors (TFETs) by technology computer aided design simulations is reported. The most interesting outcome of our design effort is a dual metal gate (DMG) TFET, which features an inverse subthreshold slope (SS) significantly < 60 mV/decade over more than five orders of magnitude of drain current, with a minimum value of 6 mV/decade sustained across one drain current decade or more. The DMGTFET simultaneously fulfills both the low-stand-by-power off-state current and the high-performance on-state current at a supply voltage of 0.5 V. Therefore, 25% reduction of static power consumption is expected compared with the 2020 International Technology Roadmap for Semiconductors requirements for multigate transistors

Boosting InAs TFET on-current above 1 mA/um with no leakage penalty

In this work, an InAs Tunnel Field-Effect-Transistor (TFET) is carefully optimized by TCAD simulations. The device is able to provide on-state currents in the mA/m range at a reduced supply voltage of 0.5 V, while keeping the off-state currents below the ITRS specs for HP and LOP devices. Next, the designed TFET is benchmarked with respect to the ITRS specs for advanced multigate transistors projected to year 2020

Optimization of a Pocketed Dual-Metal-Gate TFET by Means of TCAD Simulations Accounting for Quantization-Induced Bandgap Widening

A dual-metal-gate (DMG) tunnel FET (TFET) integrating a heavily-doped pocket within the channel is optimized through TCAD simulations by considering quantization-induced bandgap widening. First, the performance penalty due to the reduced tunneling probability is estimated and next, device design options to minimize the negative impact of quantization on the DMG-TFET performance are assessed