Effectiveness of a Preventative Program for Groin Pain Syndrome in Elite Youth Soccer Players: A Prospective, Randomized, Controlled, Single-Blind Study

: Groin pain syndrome (GPS) is a prevalent issue in soccer. This study assessed the effectiveness of a new preventive protocol on GPS for youth soccer players. The protocol included targeted stretching and strengthening exercises for the adductor and core muscles from preseason to midseason. A questionnaire and two pain provocation tests were used for the evaluation. Mild GPS required positive results in at least two evaluations, while severe GPS was associated with pain incompatible with engagement in any activity confirmed by diagnostic ultrasound. Forty-two elite male athletes (aged 16.9 ± 0.7 years) participated in the study, with half of them assigned to the usual training (control group) and the remaining athletes undergoing the preventive protocol (treatment group) for 24 weeks. GPS rates were 14.3% (three diagnoses: two mild, one severe) in the treatment group and 28.6% (six diagnoses: three mild, three severe) in the control group. Toward the end of the season, three players, one from the treatment group and two from the control group had to stop playing due to severe GPS problems. In addition, one player in the control group stopped midseason. Even though the reduction in the risk of developing GPS was not significant (relative risk of 0.50 ([95%CI 0.14 to 1.74], p = 0.2759), the halved incidence of severe GPS and the increased muscle strength related to the treatment (p = 0.0277) are encouraging data for future studies

Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications

The fractional-N frequency synthesis based on Digital Phase Locked Loop (DPLLs) has become a conventional design approach for the new radio wireless applications. The advantage of the digitally-intensive design style is the possibility to implement low-power and very accurate digital calibration techniques. Most of these algorithms run in the background tracking PVT variations and either relax or, in some cases, completely remove the performance limitations due to analog impairments. Moreover, the digital loop filter area is practically negligible with respect to the one in analog PLLs. These benefits become even more relevant in the scaled CMOS technology nodes. This chapter identifies the design parameters of a standard DPLL architecture and proposes a novel locking scheme to overcome the intrinsic limitations of the digital frequency synthesizers approach. To prove this new scheme a sub-6GHz fractional-N synthesizer has been implemented in 65nm CMOS. The synthesizer has an output frequency from 3.59GHz to 4.05GHz. The integrated output jitter is 182fs and the power consumption of 5.28mW from 1.2V power supply leads to a FoM of -247.5dB. This topology exploits a novel locking technique that guarantee a locking time of 5.6s, for a frequency step of 364MHz, despite the use of a single bit phase detector

Analysis of power efficiency in high-performance class-B oscillators

This paper presents an analysis of power efficiency in LC voltage-controlled oscillators (VCOs). Three different class-B topologies are compared under different operating conditions, demonstrating that the CMOS oscillator embedding two tail resonators achieves the best power efficiency and, consequently, best phase-noise-versus-power trade-off. A 65-nm CMOS prototype in post-layout simulations achieves a phase noise of -159 dBc/Hz at 20-MHz offset from the 3.6-GHz carrier, while dissipating 4.5 mW from 1.2-V power supply and covering 21.8% tuning range

A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity

In this paper, we present a novel input buffer based on the push-pull architecture for an 11-bit 2-GS/s 8x time-interleaved ADC. The proposed buffer features an auxiliary follower which is used to drive the body terminals of the main push-pull output transistors, removing their non-linear contribution at the output node, with a negligible overhead in terms of power consumption. The ADC features a 0.9-V reference voltage and requires an input common-mode voltage of 0. 45V. The proposed buffer, designed in a 28-nm CMOS technology, achieves better than 73-dB Spurious-Free Dynamic Range (SFDR) in the 1-GHz Nyquist bandwidth, which is up to 6.3dB better than the conventional push-pull topology, burning 38mW from +1.8/-1V supplies, including the bias circuit

A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter

Digital PLLs (DPLLs) have demonstrated to be a promising candidate to implement frequency synthesizers in wireless transceivers, thanks to their scaling-friendly architecture and to the possibility of implementing powerful background adaptive calibration algorithms to compensate the system non-idealities. The combination of these features leads to an inherently faster time-to-market than traditional analog PLLs, avoiding lengthy porting and redesign phases and factory calibrations, making DPLLs particularly attractive to cope with the surge of mobile applications recently driven by remote working and contactless businesses. Among DPLLs, bang-bang DPLLs are especially attractive for their reduced complexity and low power consumption, thanks to the use of a binary phase detector (BPD), while still capable of achieving state-of-the-art phase noise, jitter, and fast-lock performances [1]–[2]. However, the DPLL bandwidth, on top of being subject to process, voltage, and temperature (PVT) variations, also depends on the system phase noise level [3]

A Digital PLL with Multi-tap LMS-based Bandwidth Control

Automatic bandwidth control based on least-mean-square adaptive filters has been demonstrated to desensitize the loop gain of a phase-locked loop from process spreads, environmental variations and channel frequency. This work extends this concept to low-jitter designs that adopts aggressive out-of-band filtering, by introducing multi-tap adaptive filtering. The method requires no injection of a training sequence, potentially degrading phase noise, and it is particularly suitable for bang-bang PLLs whose loop bandwidth depends on input noise. A 3.7-to-4.1-GHz PLL prototype embedding a 16-tap adaptive filter for loop gain estimation demonstrates 150-kHz loop bandwidth over input noise and voltage supply variations, at 183-fs RMS integrated jitter and 5.3-mW power consumption

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range

Digital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed

Concurrent effect of redundancy and switching algorithms in SAR ADCs

This paper analyses for the first time from a quanti-tative standpoint the effectiveness of redundancy in successive ap-proximation register (SAR) analog-to-digital converters (ADCs) that employ the conventional and monotonic switching algo-rithms. It is shown that the redundancy tolerance window is one-sided in the case of conventional switching algorithm, thus only underestimations of the input signal can be corrected. Conversely, the monotonic switching algorithm shows a symmetric tolerance window that allows the correction of both underestimations and overestimations of the input signal. Thermal noise due to switches and comparator, and supply bouncing cause both these errors and they can be effectively corrected only with a symmetric redundant window. Behavioral simulations confirm that the monotonic switching algorithm applied to redundant SAR ADCs achieves better performance than the conventional one in terms of signal-to-noise-and-distortion ratio (SNDR)

A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

This paper describes a 23-GHz digital bang-bang phase-locked loop (PLL) fabricated in 65-nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented circuit aims to generate a fast sawtooth chirp signal that grants significant advantages with respect to the more conventional triangular waveform. Such a signal, however, features a very large bandwidth that requires the adoption of a two-point injection scheme. This paper, after intuitively discussing how the nonlinearity of the digitally controlled oscillator affects the accuracy of frequency modulation, presents a novel automatic pre-distortion engine, operating fully in background, which linearizes the tuning characteristic. The 19.7-mA fractional-N PLL having an rms jitter of 213 fs and an in-band fractional spur of -58 dBc is capable of synthesizing fast chirps with 173-MHz/μs maximum slope and an idle time of less than 200 ns after an abrupt frequency step with no over or undershoot

A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation

Frequency-modulated continuous-wave (FMCW) radars with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems, the spot phase noise of the chirp generator is converted to the intermediate frequency of the receiver making it difficult to detect two close targets, while spurs cause the detection of false targets. For those reasons, medium-range radar applications in the 77-to-81GHz band typically specify spot phase noise lower than −90dBc/Hz at 1MHz offset and spur level below −50dBc. Unlike triangular chirps, saw-tooth chirps allow for a reduced dead time for range detection. However, any practical modulator needs a finite time (idle time) to make a large frequency jump at the end of the saw-tooth, and this limits the duty cycle of the saw-tooth. For instance, a fast saw-tooth chirp with 200kHz rate and 95% duty cycle leaves the idle time of only 250ns. Fractional-N PLLs can be used as chirp modulators. Unfortunately, low phase noise and spur levels require a narrow PLL bandwidth, while short idle time demands for a wide one. The two-point injection of the modulation signal, both from the modulus control of the divider and the tuning input of the voltage-controlled oscillator (VCO), is a known method to simultaneously achieve a narrow PLL bandwidth and fast modulation. However, even in that scheme, a frequency modulation error is mainly limited by gain mismatch between the two injection paths and by the linearity of the VCO [2]. In this work, a 20-to-24GHz digital bang-bang PLL, which uses the two-point modulation scheme to generate triangular and saw-tooth chirp signals, is presented. Unlike previous works [1-4], this architecture is able to generate fast saw-tooth chirps with the slope up to 173MHz/js, the idle time below 200ns, and the rms frequency error of better than 0.06%. The gain mismatch between the two modulation paths are automatically calibrated by a digital algorithm [5], and the input of the digitally controlled oscillator (DCO) is pre-distorted via an automatic background correction scheme, which compensates for the DCO nonlinearity