Round-Trip Energy Efficiency and Energy-Efficiency Fade Estimation for Battery Passport

The battery passport is proposed as a method to make the use and remaining value of batteries more transparent. The future EU Battery Directive requests this passport to contain the round-trip energy efficiency and its fade. In this paper, an algorithm is presented and demonstrated that estimates the round-trip energy efficiency of a battery pack. The algorithm identifies round trips based on battery current and SoC and characterizes these round trips based on certain conditions. 2D efficiency maps are created as a function of the conditions `temperature' and `RMS C-rate'. The maps are parameterized using multiple linear regression, which allows comparison of the efficiency under the same conditions. Analyzing data from three battery-electric buses over a period of 3.5 years reveals an efficiency fade of up to 0.86 percent point.Comment: 6 pages, 5 figures, presented at VPPC 202

An enhanced switching policy for buck-derived multi-level switching power amplifiers

This work proposes a switching policy for multi-level fullbridge switching power converters and analyses their performance by driving them with a multi-level PWM modulation, targeting highefficiency power amplifiers. Unlike conventional policies, which generate the output voltage levels only from the values of the supply voltages, this enhanced policy also uses the values of the voltage difference between supply voltages to generate additional output voltage levels, therefore maximising the number of output voltage levels for a given set of supply voltages and connection switches. Simulation results show that, when tracking a band-limited signal, the proposed switching policy can reduce the power of the high-frequency spectral content from 21% to 11% by upgrading a 5-level amplifier to a 7-level amplifier without adding supply voltages or connection switches.Peer ReviewedPostprint (published version

Integration trends in monolithic power ICs: Application and technology challenges

\u3cp\u3eThis paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions in advanced CMOS nodes. The need to combine high-density digital circuits, power-management circuits, and robust interfaces in a single technology platform requires the development of additional process options on top of baseline CMOS. Examples include high-voltage devices, devices to enable area-efficient ESD protection, and integrated capacitors and inductors with high quality factors. The use of bipolar devices in these technologies for protection and control purposes in power applications is also addressed.\u3c/p\u3

On trade-offs between computational complexity and accuracy of electrochemistry-based battery models

In this paper, we propose several simplifications to the so-called Doyle-Fuller-Newman (DFN) model, which is a popular electrochemistry-based battery model. This simplified DFN (SDFN) model allows for a computationally very efficient implementation. The simplifications are a result of several assumptions, which will be justified for two different parameter sets. Finally, the SDFN model proposed is compared to the DFN model as well as an implementation of the single-particle model, for the two parameter sets. This will show that by making specific assumptions, simplifications can be made that have no significant impact on the model accuracy, while the computation time can be drastically decreased. This leads to a simulation time of over 3600 times faster than real-time

State-of-the-art of integrated switching power converters

This paper discusses the state-of-the-art of integrated switched-capacitor and inductive power converters. After introducing applications that drive the need for integrated switching power converters, implementation issues to be addressed for integrated switched-capacitor and inductive converters are given, as well as design examples. At the end of the paper, various integrated power converters are compared in terms of the main specifications

Ageing-Aware Charging of Lithium-ion Batteries Using a Surrogate Model

In this paper, we present an optimal-control-based method for ageing-aware charging. A surrogate modeling approach is used to approximate ageing-related Doyle-Fuller-Newman (DFN) model states, where the surrogate model is a combination of a black-box finite-dimensional linear-time-invariant model and a static nonlinear model that is a function of state-of-charge. We formulate the optimal-control problem as minimizing the side reactions for a given charging time and subject to several ageing-related constraints that are commonly used in literature. We will show that the ageing-related DFN model states can be well approximated by the proposed surrogate model. Furthermore, we will show that with the surrogate modeling approach, even in an open-loop execution of the optimal-control-based method, the considered constraints are only marginally violated when applied to the DFN model. Finally, we will compare the Pareto front achieved with the proposed optimal-control-based method with the Pareto fronts achieved with various multi-stage charging protocols. Here, we will show that the proposed optimal-control-based method achieves a significantly improved Pareto front over the multi-stage charging protocols

Ageing-aware charging of lithium-ion batteries using an electrochemistry-based model with capacity-loss side reactions

In this paper, we utilize a Doyle-Fuller-Newman (DFN) model including capacity-loss side reactions to present a model-based design method for multi-stage charging protocols. This design method allows making a trade-off between charging time and battery ageing in a more systematic way. The results are leveraged by a highly efficient implementation of the DFN model, that has a short computation time. We show that by obtaining the Pareto front that describes the optimal trade-off between charging time and battery ageing for a single cycle, the results can be extended to the lifetime of the battery. Finally we show that the negative electrode over-potential is not always a good indicator for ageing, and that ageing will occur even when the battery operates in over-potential regions that are considered to not lead to ageing

A 1W 8-ratio switched-capacitor boost power converter in 140nm CMOS with 94.5% efficiency, 0.5mm thickness and 8.1mm2 PCB area

This paper presents a boost switched-capacitor power converter (SCPC) in 140nm CMOS converting a wide input voltage range (2.6V to 4.2V) to an output voltage of 5V at 1W output power. It achieves the highest applicable number of conversion ratios with the lowest number of floating capacitors to date. With 8 conversion ratios and only 4 small floating capacitors, a high peak efficiency of 94.5%, a very small PCB area of 8.1mm2, and a low thickness of 0.5mm are achieved