Development of polycrystalline silicon waveguides by laser crystallization

Silicon (Si) is an excellent material for integrated photonics devices as its high refractive index allows for small device footprints. To date, most of the work in this area has leveraged the single crystal silicon-on-insulator platforms, which are relatively expensive to produce and thus drive up component costs. Here we propose an alternative method to fabricate crystalline silicon waveguides by laser processing of an amorphous starting material. As well as reducing production costs, this approach has the added advantage of removing the substrate dependence so that more flexible alternatives can be considered. This method has previously been applied to a-Si wires grown inside silica capillaries and shown to produce very large crystallites [1]. Here we demonstrate preliminary results of laser-induced crystallization of a-Si films and micro-patterned wires produced by chemical vapor deposition (CVD) on SiO2 substrates. The samples have been crystallized using a c.w. argon-ion laser at 488nm. Crystallized tracks have been written by scanning the focused beam across the samples using different laser intensities and scanning speeds. The resulting material quality is then studied using Raman spectrometry, optical and electronic microscopy and X-ray diffraction. For the planar films, we have produced crystallite sizes on the order of hundreds of nanometers to a few microns; similar to those obtained via conventional pulsed Excimer laser crystallization [2]. However, for the micro-patterned samples, we have found that it is possible to grow crystals that almost cover the entire width of the wire, over lengths of up to 18µm, considerably larger than what is typically reported for polysilicon waveguide devices [3]. Furthermore, this laser crystallization method has been observed to reform the surface of the Si wires resulting in very smooth sidewall profiles (as shown in Fig. 1) which is very important for low loss optical transmission in photonic devices

Development of low temperature fabrication processes of n-ZnO/p-Si optical switch and poly-silicon waveguides for CMOS-compatible multi-layered silicon photonics

The potential advantages and applications of Silicon Photonics (SiP) has initiated substantial research efforts. Silicon photonics has been favourably nominated to replace the current copper interconnects due to their high bandwidth, small footprint, and potentially low power consumption. However, the majority of the research into silicon photonics has been based on the silicon-on insulator (SOI) platform. The focus on the SOI platform has limited the design of silicon photonic devices to two-dimensional (2D) structures. Moreover, the fabrication of optical active devices based on silicon photonics has relied on high temperature processing that is not compatible with CMOS back-end integration. New materials that are depositable at low temperatures can offer new possibilities for multi-layered, CMOS back-end compatible, and low optical loss silicon photonic devices. In this project, zinc oxide (ZnO) was investigated as a potential low temperature material whose fabrication is compatible with CMOS technology. Specifically, the naturally n-type doped ZnO can potentially form a heterojunction with p-type silicon without the need for high temperature processing. Poly-silicon is also a depositable and CMOS compatible material that can potentially form future multi-layered silicon photonic structures. However, low optical loss in poly-silicon has been based on high-temperature processing to improve the crystallinity and roughness of the deposited material. The deposition of poly-silicon in the SiP technology have been mainly carried out using plasma-enhanced chemical vapour deposition (PECVD) and other deposition techniques remain under investigated.In this project, ZnO was, for the first time, deposited at low-temperature (150 ?C) using atomic layer deposition (ALD) on a silicon waveguide to form a heterojunction diode capable of producing optical switching in the silicon core. Optical switching in the n-ZnO/p-Si heterojunction was caused by the plasma dispersion effect. The design of the optical switch comprised a straight silicon waveguide (width = 1000 nm, height = 220 nm, slabheight = 60 nm) partially covered with a thin ZnO film (thickness = 10 nm). The commonly used highly doped p+ region were not included in the devices because of the high thermal budget (T ' 900 ?C) needed to activate the dopant. Moreover, the aluminium (Al) metal contacts were not annealed because the annealing temperature (Ts = 425?C) exceeds the high-temperature threshold (Ts = 400?C). An extinction ratio of ~ 10 dB was achieved for a 1 mm long device at 20 V forward-bias. This result can be expressed as a figure of merit of 5 dB/cm.V. The insertion loss of the device was estimated to be ~ 1:2 dB. The maximum switching speed of the devices was found to be ~1 MHz. Al-though this performance is inferior to the state-of-the-art silicon optical switches, it offers the first silicon-based electro-optical switch fabricated at low-temperatures with low insertion loss. Detailed analysis of the I-V and switching characteristics of the device revealed large series resistance and capacitance. It was also found that the switching speed is primarily governed by the RC time constant of the device rather than the minority carrier lifetime. This fact has led us to believe that the device functions as both injection and accumulation electro-absorption switch. A thin SiO2 layer is suspected to form at the ZnO/Si interface that facilitates the accumulation operation of the device and increases the RC time constant.The first low loss and low-temperature poly-silicon waveguides are demonstrated in this project. Hot-wire chemical vapour deposition (HWCVD) was used to deposit poly-silicon films at 240?C. The propagation loss of the TE mode for a 600 by 220 nm waveguide was 13:5 dB/cm. Detailed simulation analysis revealed that at least 60% of the loss was caused by the roughness of the top surface of the waveguides. The RMS roughness was measured using atomic force microscopy (AFM) and was found to be 8:9 nm. Optimisation of the design, the deposition process, and the reduction of the top surface roughness, through surface planarisation, led to a reduction in the propagation loss of the TE mode to ~8:5 dB/cm while still maintaining low deposition temperature of 360?C. The crystal volume fraction of the optimised poly-silicon film was found to be ~96%. An electro-optical switch based on ZnO and poly-silicon heterojunction was fabricated on a multi-layered poly silicon structure. However, there were problems with the metal contact pads as well as the thickness of the first poly-silicon layer. Future work will focus on improving the n-ZnO/p-Si heterojunction electro-optical performance by adapting an accumulation type structure as well as optimising the multi-layered poly-silicon platform.<br/

Low temperature hot-wire polysilicon waveguides

We fabricated and measured low loss polysilicon waveguides deposited using Hot-Wire Chemical Vapor Deposition (HWCVD) at 240 °C. The optical propagation loss was measured to be 11.9 dB/cm at lambda = 1550 nm

Hot-wire polysilicon waveguides with low deposition temperature

We fabricated and measured the optical loss of polysilicon waveguides deposited using Hot-Wire Chemical Vapour Deposition (HWCVD) at a temperature of 240°C. A polysilicon film 220 nm thick was deposited on top of a 2000 nm thick PECVD silicon dioxide. The crystalline volume fraction of the polysilicon film was measured by Raman spectroscopy to be 91%. The optical propagation losses of 400, 500, and 600 nm waveguides were measured to be 16.9, 15.9, and 13.5 dB/cm, respectively, for transverse electric (TE) mode at the wavelength of 1550 nm. Scattering loss is expected to be the major contributor to the propagation loss

Scattering loss estimation using 2D Fourier analysis and modelling of sidewall roughness on optical waveguides

We report an accurate scattering loss 3D modeling technique of sidewall roughness of optical SOI waveguides based on Fourier and Finite Difference Time Domain (FDTD) analysis methods. The Fourier analysis method is based on the image recovery technique used in magnetic resonant imaging. Losses for waveguides with isotropic and anisotropic roughness are calculated for wavelengths ranging from 1550 nm to 3800 nm and compared with reported results in literature. Our simulations show excellent agreement with published experimental results and provide an accurate prediction of roughness-induced loss of 3D arbitrary shaped optical waveguides

Electrical characteristics of top-down ZnO nanowire transistors using remote plasma ALD

Top-down fabrication is used to produce ZnO nanowires by remote plasma atomic layer deposition over a SiO2 pillar and anisotropic dry etching. Nanowire field-effect transistors (FETs), with channel lengths in the range of 1.3–18.6 µm, are then fabricated using these 80 nm × 40 nm nanowires. Measured electrical results show n-type enhancement behavior and a breakdown voltage ~75 V at all channel lengths. This is the first report of high-voltage operation for ZnO nanowire FETs. Reproducible well-behaved electrical characteristics are obtained, and the drain current scales with 1/L, as expected for long-channel FETs. A respectable ION/IOFF ratio of 2 × 106 is obtained

Broadband 2D diamond grating couplers with variable pitch

We present the design, simulation and measurements of broadband gratings couplers with a variable grating pitch. The measured 3 dB bandwidth was over 110 nm. The gratings employ diamond-shaped sub-wavelength grating (SWG) structures for dispersion control and a varying pitch along the transmission axis

Remote plasma enhanced atomic layer deposition of ZnO for thin film electronic applications

This paper describes a systematic approach to analyze the simultaneous impact of various reactant plasma parameters of remote plasma enhanced ALD (PEALD) on the ZnO thin film properties. Particular emphasis is placed on the film stoichiometry which affects the electrical properties of the thin film.Design of Experiment (DOE) is used to study the impact of the oxygen plasma parameters such as the RF power, pressure and plasma time to realize semiconductor quality of ZnO thin film. Based on the optimized plasma condition, staggered bottom-gate TFTs were fabricated and its electrical characteristics were measured

Submicron silicon waveguides and optical splitters for mid-infrared applications

We report on the design, fabrication and characterisation of submicron silicon-on-insulator strip waveguides at a 3.74 μm wavelength. Experimental results for 1x2 multi-mode interference splitters are also given.</p

Laser-induced ferroelectric domain engineering in LiNbO₃ crystals using an amorphous silicon overlayer

We report laser-induced poling inhibition and direct poling in lithium niobate crystals (LiNbO3), covered with an amorphous silicon (a-Si) light-absorbing layer, using a visible (488 nm) continuous wave (c.w.) laser source. Our results show that the use of the a-Si overlayer produces deeper poling inhibited domains with minimum surface damage, as compared to previously reported UV laser writing experiments on uncoated crystals, thus increasing the applicability of this method in the production of ferroelectric domain engineered structures for nonlinear optical applications. The characteristics of the poling inhibited domains were investigated using differential etching and piezoresponse force microscopy