A power-efficient single-chip OFDM demodulator and channel decoder for multimedia broadcasting

\u3cp\u3eA single-chip channel demodulator and decoder IC (DABchip) for consumer receiver products based on the digital audio broadcasting (DAB) standard is discussed. The challenging aspects in the design are: level of integration, silicon cost, design time, and power dissipation. DABchip is a mixed analog and digital design taking the tuner output at about 40 MHz as input, performs all signal processing needed to demodulate and decode to transport ISO-Motion Picture Experts Group (MPEG) stream, and performs all signal processing for complete receiver synchronization.\u3c/p\u3

Throughput analysis of synchronous data flow graphs

Synchronous Data Flow Graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for application mapping on platforms. Throughput analysis of these SDFGs is an important step for verifying throughput requirements of concurrent real-time applications, for instance within design-space exploration activities. Analysis of SDFGs can be hard, since the worst-case complexity of analysis algorithms is often high. This is also true for throughput analysis. In particular, many algorithms involve a conversion to another kind of data flow graph, the size of which can be exponentially larger than the size of the original graph. In this paper, we present a method for throughput analysis of SDFGs, based on explicit state-space exploration and we show that the method, despite its worst-case complexity, works well in practice, while existing methods often fail. We demonstrate this by comparing the method with state-ofthe- art cycle mean computation algorithms. Moreover, since the state-space exploration method is essentially the same as simulation of the graph, the results of this paper can be easily obtained as a byproduct in existing simulation tools