Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-power High-performance Adders

Based on the idea of sharing two adders used in the Carry Select Adder (CSA), a new design of a low-power highperformance adder is presented. The new adder is faster than a Ripple Carry Adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA

POWER EFFICIENT DESIGN OF SRAM ARRAYS AND OPTIMAL DESIGN OF SIGNAL AND POWER DISTRIBUTION NETWORKS IN VLSI CIRCUITS

UnrestrictedIn today's IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits due to temperature-induced accelerated device and interconnect aging processes, and increases the cooling and packaging costs of these circuits. This dissertation investigates different techniques for low-power design of VLSI circuits. First, power minimization of on-chip caches is investigated. In particular, a technique is proposed to reduce the active power consumption of on-chip caches by utilizing dual threshold voltages and dual oxide thicknesses. Subsequently, a novel gating technique is presented to reduce the standby leakage current in the SRAM arrays. Next, the focus of the dissertation is shifted to power minimization in signal distribution networks. First, a low-power fanout optimization technique is presented which can be utilized to reduce the power dissipation cost of distributing a signal from source to multiple destinations. Subsequently, a methodology is presented for repeater insertion for global buses which enables low-power on-chip communication. Finally, the focus of the dissertation is shifted to power delivery network design for multiple-voltage-domain circuits. First, a technique is presented to optimally select the voltage regulator modules in the power delivery network of a SoC to achieve minimum power loss in the system. Next, a novel technique is described for power delivery network design to enable dynamic voltage scaling in a SoC

Design of an Efficient Power Delivery Network in an SoC to Enable Dynamic Power Management

Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabler for the design of any DVS technique. In this paper we show how to design an efficient power delivery network for a complex system-on-achip (SoC) so as to enable dynamic power management through assignment of appropriate voltage level (and the corresponding clock frequency) to each function block in the SoC. We show that the proposed technique reduces the power loss of the power delivery network by an average of 34 % while reducing its cost by an average of 8%

Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment

Abstract: Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in very deep submicron regime. As a result, reducing the subthreshold and gate-tunneling leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual-Vt and dual-Tox assignment to reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different types of sixtransistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. Simulation results with a 65nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64Kb SRAM by more than 50%. I

Low-power fanout optimization using multiple threshold voltage inverters

This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, power, and input capacitance, the fanout tree is converted to a set of inverter chains and for each chain the optimal sizes and threshold voltages are determined. Experimental results show that using this technique, the power dissipation of fanout tree is reduced by an average of 33 % for a state-of-the-art CMOS technology

Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-power High-performance Adders

Based on the idea of sharing two adders used in the Carry Select Adder (CSA), a new design of a low-power highperformance adder is presented. The new adder is faster than a Ripple Carry Adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA. 1

Low-leakage SRAM Design with Dual Vt Transistors

Abstract- This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and deploy different types of six-transistor SRAM cells corresponding to different threshold voltage assignments for individual transistors in the cell. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs no area or delay overhead. In addition, it results only in a slight change in the SRAM design flow. Finally, it improves the static noise margin under process variations. Experimental results show that this technique can reduce the leakage-power dissipation of a 64Kb SRAM by more than 35%. 1