Parallel prefix adder design

The paper introduces two innovations in the design of prefix adder carry trees: use of high-valency prefix cells to achieve low logical depth and end-around carry adders with reduced fan-out loading (compared with the carry select and flagged prefix adders). An algorithm for generating parallel prefix carry trees suitable for use in a VLSI synthesis tool is presented with variable parameters including carry tree width, prefix cell valency, and the spacing of repeated carry trees. The area-delay design space is mapped for a 0.25 μm CMOS technology for a range of adder widths as a comparative study.Beaumont-Smith, A. ; Lim, C.-C

A VSLI chip implementation of an A/D converter error table compensator

Copyright © 2001 Elsevier ScienceError table compensation can be used to improve the spurious free dynamic range performance of high speed A/D converters. This paper gives details of an error table compensator system that uses a VLSI chip incorporating a transversal filter programmed as a wideband differentiator, additional on-chip circuits including delays and an adder, and a lookup table that is stored in external memory. The cascadable 10GOPS transversal filter differentiator chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti-symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4-2 compressors to reduce the transistor count. The chip was fabricated in a 0.35-μm CMOS process, measures 3.1 × 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz. It is shown that the error table compensation system is capable of providing between 7 and 13 dB improvement in the dynamic range of typical high-speed A/D converters. © 2001 Elsevier Science B.V. All rights reserved.A. Beaumont-Smith, J. Tsimbinos, C. C. Lim and W. Marwoodhttp://www.elsevier.com/wps/find/journaldescription.cws_home/505607/description#descriptio

Results of A/D converter compensation with a VLSI chip

© Copyright 2002 IEEEError table compensation is one technique that can be used to improve the spurious free dynamic range of high speed A/D converters. This paper gives details of an error table compensator system that uses a VLSI chip incorporating a transversal filter programmed as a wideband differentiator, some additional on chip circuits, and a lookup table that is stored in external memory. The 10 GOPS transversal filter differentiator chip was designed and fabricated in a 0.35 /spl mu/m CMOS process, has programmable tap weights, and can operate at a maximum clock rate of 200 MHz. The results of this paper show that this error table compensation system is capable of providing up to 13 dB improvement in the dynamic range of typical high speed A/D converters. This may result in more reliable detection of weak signals of interest