SMART SECURITY MANAGEMENT IN SECURE DEVICES

International audienceAmong other threats, secure components are subjected tophysical attacks whose aim is to recover the secret information theystore. Most of the work carried out to protect these components generally consists in developing protections (or countermeasures) taken one byone. But this “countermeasure-centered” approach drastically decreasesthe performance of the chip in terms of power, speed and availability.In order to overcome this limitation, we propose a complementary approach: smart dynamic management of the whole set of countermeasuresembedded in the component. Three main specifications for such management are required in a real world application (for example, a conditionalaccess system for Pay-TV): it has to provide capabilities for the chip todistinguish between attacks and normal use cases (without the help of ahuman being and in a robust but versatile way); it also has to be basedon mechanisms which dynamically find a trade-off between security andperformance; all these mecanisms have to formalized in a way which isclearly understandable by the designer. In this article, a prototype whichenables such security management is described. The solution is based ona double-processor architecture: one processor embeds a representativeset of countermeasures (and mechanisms to define their parameters) andexecutes the application code. The second processor, on the same chip,applies a given security strategy, but without requesting sensitive datafrom the first processor. The chosen strategy is based on fuzzy logic reasoning to enable the designer to describe, using a fairly simple formalism,both the attack paths and the normal use cases. A proof of concept hasbeen proposed for the smart card part of a conditional access for Pay-TV,but it could easily be fine-tuned for other applications

SOS An innovative secure system architecture

International audience`Smart On Smart' (SOS) is a project launched in 2008 and funded by the `Agence Nationale pourla Recherche'. This project aims at helping the partnershipformed by Trusted Logic, Viaccess, LIP6, and the CEA-LETI to study aninnovative secure system architecture. This architecture is based on twoparts. The first one called the host system is in charge of the mainapplication and processes the sensitive data. Connected to the host system thesecond part called the audit system is strictly dedicated to thesecurity strategy response of the whole system.The underlying idea is that such an architecture will help to build abetter secure system. For instance it becomes possible to improve theintelligence of the security policy to be able to differentiate a normalerror behaviour from a suspect one. Since the whole system's securityreliability is adjustable it becomes also possible to maximise theperformance when nonsensitive data are processed. Non repeatablebehaviour and response of the system under attack could be alsoprogrammed in order to counter the attacker.One of the main tasks is to define a hardware architecture correspondingto this concept for which a safe boundary has to be established between thetwo systems. The software part and in particular the way thesecurity policy is implemented on the audit system is also a non obvioustask especially because the overhead due to this additional auditsystem has to be the lowest possible in order to be cost-effective.We are building a proof of concept around a pay TV application. Additionalhardware features are used to emulate fault injection attacks for thedemo. We are building the hardware model on an FPGA board provingalso that such an architecture fits an FPGA based system

Efficient Partitioning Method for Distributed Logic Simulation of VLSI Circuits

International audienceDistributed simulation is expected to provide a significant speed up of simulation run time. Partitioning and load balancing are very influential factors for speed up. The paper presents an efficient partitioning method for distributed VLSI circuits simulation. The main features of this method are the use of a logic replication algorithm. A realistic cost function based on precalculated activity of the circuit using a probabilistic algorithm, and a the balance between execution cost and communication cost. A distributed simulator based on a conservative synchronization method has been used to evaluate the performance of the partitioning

Determining The Analytic Waveform of an RC-Circuit Output

International audienceIn very deep submicron technologies, the parasitic capacitor and resistance can have a significant impact on propagation delays. The Elmore delay metric is widely used due to its efficiency and ease of use. However, it is well know that this method can have significant error on large RC-circuit. In this paper, we present a new method for determining the analytic waveform of the RC-circuit outputs. The accuracy of this method is demonstrated on several large RC interconnect circuits

A Simplified Circuit to Model RC Interconnect

In very deep submicron technologies, the parasitic capacitor and resistance can have a significant impact on propagation delay and functional failure. Several methods consist in evaluating the output delay or giving an approximation of the output signal. These methods are really simple and are easily used in timing analysis. However, they are unusable in functional failure analysis such as crosstalk noise analysis

Using Node Replication to Improve Circuit's Partition in Distributed Logic Simulation

International audienc

Technique de Simulation Event-Driven en Vue d'une Simulation Mixte Efficace

National audienc

Using Node Replication to Improve Circuit's Partition in Distributed Logic Simulation

International audienc

Modeling the Effects of Input Slew Rate and Temporal Proximity of Input Transitions in Event-Driven Simulation

International audienceThis paper presents a new approach to improve the speed of switch-level timing simulation of MOS digital circuits. High performance is achieved by redefining the concept of event within the event-driven selective-trace paradigm. Unlike conventional techniques, in our approach an event occurs on an input slope change rather than a voltage change, thereby, lessening significantly the number of events to be treated during the simulation. The accuracy of this approach is improved by taking into account temporal proximity of multiple input transitions. Experimental results obtained for several circuits show significant speed-up compared to conventional switch-level timing simulation techniques