High Speed Coding Unit Depth Identification Based on Texture Image Information Using SVM

High-Efficiency Video Coding (HEVC/H.265) is a new video coding standard with half the bit rate of its predecessor, Advanced Video Coding (AVC/H.264). AVC/H.264 uses macroblocks, processing units between 4×4 and 16×16 pixels in size. H.265 uses Coding Tree Units (CTUs), a more complicated block structure that lets images be as large as 64×64 pixels. However, changing from macroblocks to coding tree units is essential for H.265 to become more efficient. Using the quadtree structure to divide the Coding Unit (CU) makes it harder for HEVC to find the optimal rate distortion. This paper presents a Support Vector Machine (SVM)-based method for finding the fastest coding unit division in intra-prediction HEVC without compromising compression efficiency. All partitions of CTU are assessed using five characteristics: Standard Deviation (SD), Root Mean Square Error (RMSE), Sub CU Complexity Difference (SCCD), Directional Complexity (DC), and Quantization Parameter (QP) to optimize the intra-prediction of HEVC in all intra-configurations. Simulations have been carried out to estimate the performance of the proposed machine learning-based algorithm using test sequences with different resolutions. Simulation results have shown that combining directional complexity and standard deviation gives a more accurate classification. SVM has been used to separate split-unsplit samples, and the standard rate-distortion optimization technique has been used to separate samples that are hard to separate. The results have shown a reduction of 67.44% in encoding time with a slight increase in bit rate

Motion estimation for video coding: efficient algorithms and architectures

The need of video compression in the modern age of visual communication cannot be over-emphasized. This monograph will provide useful information to the postgraduate students and researchers who wish to work in the domain of VLSI design for video processing applications. In this book, one can find an in-depth discussion of several motion estimation algorithms and their VLSI implementation as conceived and developed by the authors. It records an account of research done involving fast three step search, successive elimination, one-bit transformation and its effective combination with diamond search and dynamic pixel truncation techniques. Two appendices provide a number of instances of proof of concept through Matlab and Verilog program segments. In this aspect, the book can be considered as first of its kind. The architectures have been developed with an eye to their applicability in everyday low-power handheld appliances including video camcorders and smartphones