Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowires may generate large errors, while being challenging from a technological aspect. Here, we propose to extract the drift mobility in nanowires by measuring a variation of the electric current due to the presence of a magnetic field, in a specific nanowire network topology. This method overcomes the limitations inherent to the standard Hall effect technique and might open the way to a more precise and simple measurement of mobility in nanowires, still a matter of intensive research

Trans-Capacitance Modeling in Junctionless Symmetric Double Gate MOSFETs

We have developed a closed-form solution for trans-capacitances in long-channel Junctionless Double Gate MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with Technology Computer Aided Design simulations. According to this work, a complete intrinsic capacitance network is obtained, which represents an essential step towards AC analysis of circuits based on junctionless devices

Generalized Charge Based Model of Double Gate Junctionless FETs Including Inversion

In this brief, we have developed a charge-based model for the symmetric double gate junctionless FET that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a former model and aims at giving a unified description of junctionless field effect transistors beyond the domain of operation for which they have been designed. In addition to its interest for providing technology design rules, the new model is able to explain the unexpected increase in the gate capacitance when biasing the device in deep depletion

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

We investigate the technological con-strains and design limitations of ultrathin body junctionless dou- ble gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of OFF-state-current and voltages are obtained and validated with TCAD simulations. This set of analytical expressions can be used as a guideline for technology optimization of JL DG MOSFETS

Trans-Capacitance Modeling in Junctionless Gate-All-Around Nanowire FETs

In this letter, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme recently pointed out between JL NW FET and its double gate counterpart for which such a model has been proposed. This approach is validated by 3D Technology Computer Aided Design simulations and bridges the gap between the nanowire junctionless device and its application in circuits

Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology

This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the reproducibility of the process, devices having the slit width ranging from 16 nm to 400 nm were fabricated, with slit conductance in the range 0.6 to 3 milliSiemens, in agreement with the expected values. © 2011 IEEE

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

This paper aims to model asymmetric operation in double gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of compactness and coherence, such equivalence is used to develop a complete charge based model for independent double gate junctionless architectures, including mismatch in gate capacitances and material work functions