Thermal Conduction across Metal–Dielectric Sidewall Interfaces

The heat flow at the interfaces of complex nanostructures is three-dimensional in part due to the nonplanarity of interfaces. One example common in nanosystems is the situation when a significant fraction of the interfacial area is composed of sidewalls that are perpendicular to the principal plane, for example, in metallization structures for complementary metal-oxide semiconductor transistors. It is often observed that such sidewall interfaces contain significantly higher levels of microstructural disorder, which impedes energy carrier transport and leads to effective increases in interfacial resistance. The impact of these sidewall interfaces needs to be explored in greater depth for practical device engineering, and a related problem is that appropriate characterization techniques are not available. Here, we develop a novel electrothermal method and an intricate microfabricated structure to extract the thermal resistance of a sidewall interface between aluminum and silicon dioxide using suspended nanograting structures. The thermal resistance of the sidewall interface is measured to be ∼16 ± 5 m² K GW^–1, which is twice as large as the equivalent horizontal planar interface comprising the same materials in the experimental sample. The rough sidewall interfaces are observed using transmission electron micrographs, which may be more extensive than at interfaces in the substrate plan in the same nanostructure. A model based on a two-dimensional sinusoidal surface estimates the impact of the roughness on thermal resistance to be ∼2 m² K GW^–1. The large disparity between the model predictions and the experiments is attributed to the incomplete contact at the Al–SiO₂ sidewall interfaces, inferred by observation of underetching of the silicon substrate below the sidewall opening. This study suggests that sidewall interfaces must be considered separately from planar interfaces in thermal analysis for nanostructured systems

Thermal Conduction in Vertically Aligned Copper Nanowire Arrays and Composites

The ability to efficiently and reliably transfer heat between sources and sinks is often a bottleneck in the thermal management of modern energy conversion technologies ranging from microelectronics to thermoelectric power generation. These interfaces contribute parasitic thermal resistances that reduce device performance and are subjected to thermomechanical stresses that degrade device lifetime. Dense arrays of vertically aligned metal nanowires (NWs) offer the unique combination of thermal conductance from the constituent metal and mechanical compliance from the high aspect ratio geometry to increase interfacial heat transfer and device reliability. In the present work, we synthesize copper NW arrays directly onto substrates via templated electrodeposition and extend this technique through the use of a sacrificial overplating layer to achieve improved uniformity. Furthermore, we infiltrate the array with an organic phase change material and demonstrate the preservation of thermal properties. We use the 3ω method to measure the axial thermal conductivity of freestanding copper NW arrays to be as high as 70 W m^–1 K^–1, which is more than an order of magnitude larger than most commercial interface materials and enhanced-conductivity nanocomposites reported in the literature. These arrays are highly anisotropic, and the lateral thermal conductivity is found to be only 1–2 W m^–1 K^–1. We use these measured properties to elucidate the governing array-scale transport mechanisms, which include the effects of morphology and energy carrier scattering from size effects and grain boundaries