An efficient simulation of quantum error correction codes

The QCAD which has been technologically advanced during last few years to support basic transformations, simulating multi-dimensional quantum devices and circuits. It is most important to demonstrate the theoretical operation of quantum computer using the simulator. Besides of describing various noise models in terms of quantum gates, a direct support of quantum error correction codes. Using the quantum error correction codes, the effects of applying single bit or phase flip error to the quantum circuits are reported along with the error recovery method for different qubit codes. The results are generated using the QCAD simulator. A simulation model for evaluating single qubit error in the proposed quantum circuit is also given. The working software prototype of an extremely efficient quantum computer simulator which is an attractive and versatile tool for both research and education. Keywords: Qubit, Noise models, Qubit error, Quantum gate

A Vertical handoff technique using context transfer cross-layer P-SIP Scheme for IMS based LTE-WiMAX architecture: context transfer cross-layer P-SIP Scheme for IMS based LTE-WiMAX architecture

Next-generation heterogeneous wireless networks provide flexibility to access IP multimedia services (IMS) anywhere at any time and with always-on connectivity in various networks. IMS service allows to include various networks to provide seamless data services and helps to reduce the delay that occurred during the handoff process. Long-term evolution (LTE) is the fastest emerging mobile communication technology in the current networking field. We proposed an interworking architecture of LTE and Worldwide Interoperability for Microwave Access (WiMAX). The key goal is to provide seamless services in heterogeneous networks. We proposed an algorithm to reduce this IMS delay using Cross-layer and Context Transfer Prior –SIP (P-SIP) scheme using Media Independent Handover (MIH) services. Performance metrics of Integrated LTE- WiMAX architecture in terms of VHO latency, signaling overhead cost, and packet loss are analyze