Status and Prospects of ZnO-Based Resistive Switching Memory Devices

In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges

An ultra low-energy DAC for successive approximation ADCs

An ultra low-energy successive approximation (SA) Analog-to-Digital Converter (ADC) is presented. The proposed ADC uses an energy-efficient unit capacitor array having a new switching arrangement in DAC for passive charge re-distribution. Reference levels are generated sequentially to get successive bits. The proposed method is analyzed theoretically and compared with other methods. Mathematical analysis shows that energy dissipation per bit can be reduced to the minimum possible normalized level, which is approximately 200 times lower than reported theoretical values. Simulation results of the proposed DAC in 90nm UMC MM CMOS process are also presented

Robust Soft Error Tolerant CMOS Latch Configurations

This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor building block called 1P-2N and its complementary block 2P-1N. It is shown that all proposed latches have better soft error rate (SER) performance as compared to the SE-tolerant latches reported till date. It is also shown that the proposed configurations provide a more relaxed tradeoff between SER and other specifications mainly delay, power dissipation and area. RTL implementation of a proposed latch is also shown to verify the behaviour subjected to the transient faults. The benefit of implementing a SE tolerant circuit in VHDL language is the feasibility to exhaustively check the immunity of the circuit against transient faults at every sensitive node by just writing simple boolean expressions of each element in the circuit. The proposed configurations and a few selected reported configurations have been also designed, laid out and post layout extracted in 90 nm CMOS logic technology. Post layout simulations have been performed on all proposed latch configurations with clock frequency of 500 MHz and performance comparison results are presented

6-bit low-power subranging-ADC with increased throughput

This paper describes a high-speed low-power subranging Flash ADC designed in 90nm Mixed-Mode CMOS process. The maximum speed of subranging-ADC is limited by the time taken for the fine-ADC reference to settle. The proposed method splits optimally the total time taken for the coarse-ADC and fine-ADC comparisons to achieve the maximum possible clock speed. An auxiliary track-and-hold has been used in the interleaved track-and-hold to introduce 1/2 clock-cycle delay. Simulations results show that the subranging-ADC achieves SFDR of 37.7 dB at sampling rate of 1.54GS/s for 360MHz input and dissipates 15 mW power from I-V supply. It has 4.6 ENOB @ Nyquist and FoM of 0.4 pJ/conv. step. Minimum-size devices have been used in the comparator to achieve low-power. A digital offset calibration method has been used to reduce the offset of comparators

Experimental study for selection of electrode material for ZnO-based memristors

The fabrication and characterisation of 400 nm-thick zinc oxide (ZnO)-based memristor devices with platinum (Pt), chromium (Cr) and gold (Au) metal electrodes are presented. The effect of these electrode materials on the performance of ZnO-based memristors has been experimentally studied. Metal/ZnO contact limits the memristor switching mechanism, dominating during the resistive switching. It is observed that the ZnO-based memristor with the Pt electrode shows a better hysteresis compared to Cr and Au metal electrodes. In the case of the Pt electrode, a current ratio of six times in magnitude is observed between the high resistive state and low resistive state at 1 V, where a maximum current density value of 1.25 A/cm(2) is measured. The capacitance of these devices strongly depends on the charge distributed on the surface. Therefore, the capacitance-voltage (C-V) behaviour can be used to understand the charge distribution, under various bias conditions. The C-V behaviour of the Pt memristor, so as to understand the contact interface, where the maximum capacitance of 2.3 x 10(-7) F/cm(2) is obtained at 0 V, is also explained

Impact of technology scaling on metastability performance of CMOS synchronizing latches

In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are τm and Tw. τm is the exponential time constant of the rate of decay of metastability and T w is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that τm scales better than the technology scale factor. Tw also scales down but its factor cannot be estimated as well as that of τ m. This is because Tw is a complex function of signal and clock edge rate and logic threshold level.© IEE

A survey of bandgap and non-bandgap based voltage reference techniques

The design challenges of voltage reference generators in CMOS technology have increased over the years in low-voltage low-power CMOS integrated circuits, constituting analog, digital, and mixed-signal modules. The emergence of hand-held power autonomous devices pushes the power consumption limit to nW regime. Along with these confrontations, limited full-scale range of data converters at low supply levels demands accurate reference voltage generators. This paper reviews the allied design challenges and discusses the evolved methodologies to tackle them. This paper also prominently surveys the sub-1 V voltage reference topologies presented in the literature along with classic bandgap based voltage reference topologies. Non-bandgap (only CMOS) based reference architectures are proven to be area-and power-e ffi cient, but always have to be accompanied with auxiliary on/off chip trimming mechanism for high accuracy. We also provide insightful analysis of the voltage reference topologies required by the designers. (C) 2016 Sharif University of Technology. All rights reserved

Comments on "An Analog 2-D DCT Processor"

In the paper "An analog 2-D DCT processor," authors have presented a row-column method for computing 2-D discrete cosine transform (DCT). They have reported minimum peak signal-to-noise ratios (PSNR) 40.6 dB and 31.4 dB for 4-point and 8-point DCT, respectively. The main objective of this comment letter is to point out that those PSNR values are not correctly calculated. The actual minimum PSNR values are shown to be 24.7 dB and 22.7 dB for 4-point and 8-point DCT, respectively. Similarly, maximum PSNR values are corrected in this letter

Investigations on magnetic characteristics of the soil and their influence on its dielectric response

Conventionally, soils have been characterized based on their physical, chemical and mineralogical characteristics. However, in order to address various geo-environmental issues that have become a threat for the modem day civilization, soils have also been characterized based on their electrical properties. Furthermore, it has been demonstrated that the electrical properties of the soil mass (i.e., the soil compacted at a certain dry density and water content) are instrumental, primarily, in measuring its volumetric moisture content. In this context, though several efforts have been made by earlier researchers to determine dielectric response of the soil mass, the effect of soil magnetic characteristics on dielectric response and volumetric moisture content has not been established yet. Hence, development of a methodology to determine magnetic characteristics and their relationship with the dielectric response of the soil mass, if any, becomes quite intriguing. With this in view, soils of entirely different characteristics were tested for their magnetic characteristics (viz., remnant magnetization, coercivity and magnetic hysteresis area) by employing a magnetometer. Furthermore, these characteristics have been correlated with the physical, chemical, mineralogical and electrical properties (dielectric dispersion obtained from an impedance analyzer) of the soil. The study demonstrates that the parameter "area of magnetic hysteresis" of the air dried soils has significant influence on soil specific parameters such as specific gravity, iron content and dielectric constant. This preliminary study also proposes a hypothesis to obtain volumetric moisture content of the soil mass based on its magnetic characteristics and dielectric constant, which can be obtained from an impedance analyzer. However, efficiency and utility of the proposed hypothesis should be demonstrated by testing a large number of soils from different parts of the world

Compensation of temperature effects for in-situ soil moisture measurement by DPHP sensors

Dual probe heat pulse (DPHP) sensors are economical solutions for soil moisture measurements. However, in agriculture fields the temperature significantly changes from time to time during 24 h, which affects response of the soil moisture sensor. This paper, analyzes and models the error produced in the response of the DPHP sensors due to variation of the soil temperature. For this purpose, first effect of the soil temperature on the response of the sensor is studied using eight different soil samples. Accordingly, the existing soil moisture model, used for DPHP devices, is modified and used for the temperature compensation. A low power DPHP sensor comprising one heater probe and one temperature sensor probe, placed 0.003 m apart, is fabricated. A low power, automated system, dissipating average power of 30 mW, is also developed for the field measurements to validate the proposed model. The developed system is deployed in the field and soil moisture is measured for 38 h at every 1 h interval. Field measurements indicates that volumetric moisture content measured without temperature compensation leads to error of about 3% and with temperature compensation the error is reduced to 0.5%. (C) 2017 Elsevier,B.V. All rights reserved