Embedded computing New directions in architecture and automation

SIGLEAvailable from British Library Document Supply Centre-DSC:4335.26205(2000-115) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

High-level synthesis of nonprogrammable hardware accelerators

SIGLEAvailable from British Library Document Supply Centre-DSC:4335.26205(2000-31) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

HPL-PD architecture specification Version 1.1

This is a revised version of technical report HPL-93-80, February 1994SIGLEAvailable from British Library Document Supply Centre-DSC:4335.26205(93-80(R.1)) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats

SIGLEAvailable from British Library Document Supply Centre-DSC:4335.26205(2000-141) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

A constructive solution to the juggling problem in systolic array synthesis

SIGLEAvailable from British Library Document Supply Centre-DSC:4335.26205(2000-30) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Fast design space exploration through validity and quality filtering of subsystem designs

SIGLEAvailable from British Library Document Supply Centre-DSC:4335.26205(2000-98) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Profile-Driven Instruction Level Parallel Scheduling with Application to Super Blocks

Code scheduling to exploit instruction level parallelism (ILP) is a critical problem in compiler optimization research, in light of the increased use of long-instruction-word machines. Unfortunately, optimum scheduling is computationally intractable, and one must resort to carefully crafted heuristics in practice. If the scope of application of a scheduling heuristic is limited to basic blocks, considerable performance loss may be incurred at block boundaries. To overcome this obstacle, basic blocks can be coalesced across branches to form larger regions such as super blocks. In the literature, these regions are typically scheduled using algorithms that are either oblivious to profile information (under the assumption that the process of forming the region has fully utilized the profile information), or use the profile information as an addendum to classical scheduling techniques. We believe that even for the simple case of linear code regions such as super blocks, additional performanc..