Scattering mechanisms in MOS/SOI devices with ultrathin semiconductor layers

Main scattering mechanisms affecting electron transport in MOS/SOI devices are considered within the quantum-mechanical approach. Electron mobility components (i.e., phonon, Coulomb and interface roughness limited mobilities) are calculated for ultrathin symmetrical DG SOI transistor, employing the relaxation time approximation, and the effective electron mobility is obtained showing possible mobility increase relative to the conventional MOSFET in the range of the active semiconductor layer thickness of about 3 nm

Electron mobility and drain current in strained-Si MOSFET

Electron mobility and drain current in a strained-Si MOSFET have been calculated and compared with the mobility and drain current obtained for the relaxed material. In the first step, our mobility model has been calibrated to the "universal mobility" according to the available experimental data for unstrained Si MOSFETS. Then, employing the mobility parameters derived in the calibration process, electron mobility and the drain current have been calculated for strained-Si MOSFETs

Comparison of gate leakage current components in metal-insulator-semiconductor structures with high-k gate dielectris

Numerical simulations of the gate leakage current in metal-insulator-semiconductor (MIS) structures based on the transfer matrix approach were carried out. They show contribution of different components of this current in MIS structures with best known high-k dielectrics such as Ta2O5 and TiO2. The comparison of the gate leakage current in MIS structures with SiO2 layer as well Ta2O5 and TiO2 layers is presented as well. Additionally, the minimum Si electron affinity to a gate dielectric which allows to preserve given level of the gate leakage current is proposed

Modeling and simulation approaches for gate current computation

This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future – in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy