Vertical Strained Impact Ionization MOSFET (VESIMOS) Technology Approach for Based Biosensor Applications using its Behavioral Model

This paper gives an overview about uniqueness characteristics of Vertical Strained Impact Ionization MOSFET (VESIMOS) technology act as bio-sensing devices. There are three proposed devices used VESIMOS technology which are Single Channel VESIMOS (SC-VESIMOS), Dual Channel (DC-VESIMOS), VESIMOS Incorporating Dielectric Pocket (VESIMOS-DP) are probably can become feasible candidates as biosensor devices. The selected devices from three structures was further analyzed for its behavioral model. The extracted parameter from the device simulations was used to design the circuitry model to represent the characteristic and behavior of the selected devices in circuit implementation. The best characteristic of the device shown by DC-VESIMOS and selected for further analysis. The behavioral model or equivalent circuit model of DC-VESIMOS used PSPICE circuit simulator. Main prerequisite of biosensor device are high sensitivity, faster response, and high reliability which represented by the VESIMOS structures. Low subthreshold swings present the sensitivity of the devices shown by DC-VESIMOS are 11.48 mV/dec and 10.53 mV/dec from TCAD and PSPICE results respectively

Equivalent circuit model analysis of vertical impact ionization MOSFET (IMOS)

In this paper, an equivalent circuit model is proposed that describes the avalanche and snapback characteristics of Vertical Impact Ionization MOSFET (IMOS). The equivalent circuit model is constructed using MOS transistors that represent the avalanche characteristics. The main goal is to predict the vertical IMOS integrated circuits by using circuit simulations. The vertical IMOS is predicted to have a lower subthreshold slope and high ratio of current. Besides that, the equivalent circuit model is explained which is include the parasitic bipolar transistor with a generated-hole-dependent base resistance. The models for parasitic bipolar is combined with a PSPICE MOS transistor model and it is represented the gate bias dependence of snapback characteristic. The equivalent circuit parameters are extracted from the reference experimental values of previous research and modified to reproduce the measured avalanche and snapback characteristic of the vertical IMOS transistor. The results show that 90% of the analysis subthreshold slope value of circuit simulations similar to the reference experimental value. The ratio of the current also shows almost the same behavior. Therefore, the equivalent circuit model for vertical IMOS can be used in circuit simulations