Algorithm transformation methods to reduce the overhead of software-based fault tolerance techniques

This paper introduces a framework that tackles the costs in area and energy consumed by methodologies like spatial or temporal redundancy with a different approach: given an algorithm, we find a transformation in which part of the computation involved is transformed into memory accesses. The precomputed data stored in memory can be protected then by applying traditional and well established ECC algorithms to provide fault tolerant hardware designs. At the same time, the transformation increases the performance of the system by reducing its execution time, which is then used by customized software-based fault tolerant techniques to protect the system without any degradation when compared to its original form. Application of this technique to key algorithms in a MP3 player, combined with a fault injection campaign, show that this approach increases fault tolerance up to 92%, without any performance degradation

HETA: hybrid error-detection technique using assertions

This paper presents HETA, a hybrid technique based on assertions and a non-intrusive enhanced watchdog module to detect SEE faults in microprocessors. These types of faults have a major influence in the microprocessor’s control flow, causing incorrect jumps in the program’s execution flow. In order to protect the system, a non-intrusive hardware module is implemented in order to monitor the data exchanged between the microprocessor and its memory. Since the hardware itself is not capable of detecting all control flow errors, it is enhanced to support a new software-based technique. Also, previous techniques are used to reach higher detection rates. A fault injection campaign is performed using a MIPS microprocessor. Simulation results show high detection rates with a small amount of performance degradation and area overhead

Exploring the limitations of software-based techniques in SEE fault coverage

This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of a MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions may lead designers into developing more efficient techniques to detect these types of faults

Detecting SEEs in microprocessors through a non-intrusive hybrid technique

This paper presents a hybrid technique based on software signatures and a hardware module with watchdog and decoder characteristics to detect SEU and SET faults in microprocessors. These types of faults have a major influence in the microprocessor’s control-flow, affecting the basic blocks and the transitions between them. In order to protect the transitions between basic blocks a light hardware module is implemented in order to spoof the data exchanged between the microprocessor and its memory. Since the hardware alone is not capable of detecting errors inside the basic blocks, it is enhanced to support the new technique and then provide full control-flow protection. A fault injection campaign is performed using a MIPS microprocessor. Simulation results show high detection rates with a small amount of performance degradation and area overhead

Evaluating selective redundancy in data-flow software-based techniques

This paper presents an analysis of the efficiency of using selective redundancy applied to registers in software-based techniques. The proposed selective redundancy chooses a set of allocated registers to be duplicated in software in order to provide detection of upsets that occur in the processor hardware and provokes data-flow errors. The selective redundancy is implemented over miniMIPS microprocessor software. A fault injection campaign is performed by injecting single event effect upsets in the miniMIPS hardware. Results show error detection capability, performance degradation and program memory footprint for many case studies. With that, designers can find the best trade-off in using selective redundancy in software

Evaluating neutron induced SEE in SRAM-based FPGA protected by hardware- and software-based fault tolerant techniques

This paper presents an approach to detect SEEs in SRAM-based FPGAs by using software-based techniques combined with a nonintrusive hardware module. We implemented a MIPS-based soft-core processor in a Virtex5 FPGA and hardened it with software- and hardware-based fault tolerance techniques. First fault injection in the configuration memory bitstream was performed in order to verify the feasibility of the proposed approach, detection rates and diagnosis. Furthermore a neutron radiation experiment was performed at LANSCE. Results demonstrate the possibility of employing more flexible fault tolerant techniques to SRAM-based FPGAs with a high detection rate. Comparisons between bitstream fault injection and radiation test is also presented

Analyzing the effects of TID in an embedded system running in a flash-based FPGA

This work analyzes the behavior of a designed embedded system composed of microprocessor, memories and SpaceWire (SpW) links under Total Ionizing Dose (TID) synthesized into a commercial flash-based FPGA from Actel. Two tests were performed: one the FPGA is configured just once at the beginning of the irradiation and the other the FPGA is reconfigured every 5 krad (Si). Results evaluate power supply current (Icc), temperature, function operation and performance degradation

A fault tolerant approach to detect transient faults in microprocessors based on a non-intrusive reconfigurable hardware

This paper presents a non-intrusive hybrid fault detection approach that combines hardware and software techniques to detect transient faults in microprocessors. Such faults have a major influence in microprocessor-based systems, affecting both data and control flow. In order to protect the system, an application-oriented hardware module is automatically generated and reconfigured on the system during runtime. When combined with fault tolerance techniques based on software, this solution offers full system protection against transient faults. A fault injection campaign is performed using a MIPS microprocessor executing a set of applications. HW/SW implementation in a reprogrammable platform shows smaller memory area and execution time overhead when compared to related works. Fault injection results show the efficiency of this method by detecting 100% of faults