NOVATEUR PUBLICATIONS INTERNATIONAL JOURNAL OF INNOVATIONS IN ENGINEERING RESEARCH AND TECHNOLOGY [IJIERT] Design of carry save adder using transmission gate logic

ABSTRACT In this paper Carry Save Adder has been implemented. The comparison is done on the basis of two performances such as area, power consumption. The full adder cells for low power applications have been implemented using transmission gate based technique for sum and carry operation. In this paper transmission gate also used. It used to minimize the transistor count. By using the transmission gate the transistor count has decreased thereby the total chip area gets minimized and the power consumption also gets reduced