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1 research outputs found
Variable Latency approach in VLSI adder Implemented to Reduce Area and Power
Author
Arulpriya S Davood KS.
Dao H Oklobdzija VG.
+17Â more
Dimitrakopoulos G Nikolos D.
Iyer A Kumar PH, Jayasurya P, Karpagam M, Kaarthik K.
Kaarthik K Pradeep S, Selvi S.
Kaarthik K Vivek C.
Kaarthik K Vivek C.
Kaur J Sood L.
Mondal SR Bhowmik M, Maity S, Sultana R.
Rajarajachozhan C Daniel Raj A, Deb S.
Singh S Kumar D.
Swapna K. Gedam and Pravin P.
Uma R Vijayan V, Mohanapriya M, Paul S.
Vishwaja S Kaarthi K.
Vivek C Rajan SP, Kavitha V.
Vivek C Rajan SP.
Vivek C Rajan SP.
Vivek C Rajan SP.
Ziegler MM Stan MR.
Publication venue
'Indian Society for Education and Environment'
Publication date
Field of study
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