Detecting Resistive-Opens in RRAM using Programmable DfT Scheme

Resistive Random Access Memory (RRAM) is one of the emerging memory devices that possesses a combined attribute of SRAM, DRAM and flash. How- ever, as the technology and fabrication process of such a promising memory devices are still immature, RRAM is expected to be impacted by process-variation faults such as resistive-open. This kind of defect is difficult to be detected using existing Design-for-Testability (DfT) scheme, which is developed based on a single critical defect value. This paper presents a new DfT scheme with the capability to identify faulty RRAM cells impacted by resistive-opens due to process variation. The new DfT scheme, referred to as Programmable Low Write Voltage (PLWV), is based on multiple voltage levels that can be programmed to suit the target fault coverage. The concept, design methodology and circuit are described. SPICE simulation results suggest that the proposed PLWV scheme can detect faults with different defect values at minimal circuit modification

A New Test Scheme for Process Variation-Induced Faults in Resistive RAMs

Resistive random access memory (RRAM) is vying to be one of the main universal memories for computing systems. Nonetheless, due to infancy knowledge and technology to fabrication RRAM, this emerging memory technology is expected to be impacted by processvariation-induced faults. Due to their varying behavior, processvariation-inducedfaults are problematic to be detected using existing test approach that is solely based on the March test concept. This manuscript presents a new test scheme based on the combination of the Design-for-Testability (DfT) concept with the March test concept to detect such faults. Unlike the conventional DfT that asserts a single, fixed write voltage during testing, the proposed test scheme asserts multiple voltage levels that can be digitally adjusted. Simulation results using Verilog-AMS and HSPICE tools show that the process variation-induced faults can be detected with minor circuit modification. In addition, as the proposed test approaches are programmable, the proposed test scheme alleviates the redesign phase and in turn accelerates time-to-market