Algebraic symmetries of generic (m+1)(m+1) dimensional periodic Costas arrays

In this work we present two generators for the group of symmetries of the generic $(m+1)$ dimensional periodic Costas arrays over elementary abelian $(\mathbb{Z}_p)^m$ groups: one that is defined by multiplication on $m$ dimensions and the other by shear (addition) on $m$ dimensions. Through exhaustive search we observe that these two generators characterize the group of symmetries for the examples we were able to compute. Following the results, we conjecture that these generators characterize the group of symmetries of the generic $(m+1)$ dimensional periodic Costas arrays over elementary abelian $(\mathbb{Z}_p)^m$ groups

Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs

The enumeration of two-dimensional Costas arrays is a problem with factorial time complexity and has been solved for sizes up to 29 using computer clusters. Costas arrays of higher dimensionality have recently been proposed and their properties are beginning to be understood. This paper presents, to the best of our knowledge, the first proposed implementations for enumerating these multidimensional arrays in GPUs and FPGAs, as well as the first discussion of techniques to prune the search space and reduce enumeration run time. Both GPU and FPGA implementations rely on Costas array symmetries to reduce the search space and perform concurrent explorations over the remaining candidate solutions. The fine grained parallelism utilized to evaluate and progress the exploration, coupled with the additional concurrency provided by the multiple instanced cores, allowed the FPGA (XC5VLX330-2) implementation to achieve speedups of up to 30× over the GPU (GeForce GTX 580)

Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs

The enumeration of two-dimensional Costas arrays is a problem with factorial time complexity and has been solved for sizes up to 29 using computer clusters. Costas arrays of higher dimensionality have recently been proposed and their properties are beginning to be understood. This paper presents, to the best of our knowledge, the first proposed implementations for enumerating these multidimensional arrays in GPUs and FPGAs, as well as the first discussion of techniques to prune the search space and reduce enumeration run time. Both GPU and FPGA implementations rely on Costas array symmetries to reduce the search space and perform concurrent explorations over the remaining candidate solutions. The fine grained parallelism utilized to evaluate and progress the exploration, coupled with the additional concurrency provided by the multiple instanced cores, allowed the FPGA (XC5VLX330-2) implementation to achieve speedups of up to 30× over the GPU (GeForce GTX 580)

Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures

The achievement of effective implementations to multi-FPGA architectures is greatly dependent on the process of partitioning. Although several automated high-level partitioning (HLP) methods have been reporte

An assessment of high-level partitioning techniques for implementing discrete signal transforms on distributed hardware architectures

Abstract — Partitioning is an essential step in the implementation of algorithms to distributed hardware architectures (DHAs) such as multi-FPGA boards. While numerous approaches working at the structural level have been reported, techniques targeted at higher levels are less common. Moreover, when dealing with discrete signal transforms (DSTs), formulation-level partitioners for DHAs have been largely neglected. In this paper, we introduce a first approach towards a functionally-aware methodology that could provide improved results for the high-level partitioning of DSTs to DHAs. Our methodology has been devised through the study of DST partitioning techniques for DHA-similar systems, as well as general DST formulation techniques. An assessment performed on discrete Fourier transforms has achieved as much as 35 % in latency reduction when compared to other general, high-level partitioning schemes. I

Functionally-aware Partitioning of Discrete Signal Transforms for Distributed Hardware Architectures ∗

Abstract — A high-level partitioning methodology is introduced, which uses formulation-level discrete signal transform properties to provide improved results for their partitioning to distributed hardware architectures. We discuss how discrete signal transform characteristics were taken into account to focus design exploration during partitioning. Additionally, a description is given of the experiments conducted to determine the effect of formulation-level properties on solution quality. Perceived patterns in experimental results were used to generate ‘partitionfriendly’ formulations for distributed hardware architectures. I