Innovative methods for Burn-In related Stress Metrics Computation

Burn-In equipment provide both external and internal stress to the device under test. External stress, such as thermal stress, is provided by a climatic chamber or by socket-level local temperature forcing tools, and aims at aging the circuit material, while internal stress, such as electrical stress, consists in driving the circuit nodes to produce a high internal activity. To support internal stress, Burn-In test equipment is usually characterized by large memory capabilities required to store precomputed patterns that are then sequenced to the circuit inputs. Because of the increasing complexity and density of the new generations of SoCs, evaluating the effectiveness of the patterns applied to a Device under Test (DUT) through a simulation phase requires long periods of time. Moreover, topology-related considerations are becoming more and more important in modern high-density designs, so a way to include this information into the evaluation has to be devised. In this paper we show a feasible solution to this problem: the idea is to load in the DUT a pattern not by shifting inside of it a bit at a time but loading the entire pattern at once inside of it; this kind of procedure allows for conservative stress measures, thus it fits for stress analysis purposes. Moreover, a method to take the topology of the DUT into account when calculating the activity metrics is proposed, so to obtain stress metrics which can better represent the activity a circuit is subject to. An automotive chip accounting for about 20 million of gates is considered as a case of study. Resorting to it we show both the feasibility and the effectiveness of the proposed methodology

ICS2 - Industry Case-Study Presentations Session 2

Evaluating Burn-In related Metrics for large Automotive Systems-on-Chip. Francesco ANGIONE1, Paolo BERNARDI1, Andrea CALABRESE1, Stefano QUER1, Davide APELLO2, Vincenzo TANCORRE2, Roberto UGIOLI2 1Politecnico di Torino, Italy, 2STMicroelectronics, ItalyMBSA Approaches Applied to Next Decade Digital Components. Tiziano FIORUCCI1, Jean-Marc DAVEAU1, Emmanuel ARBARETIER2, GIORGIO DI NATALE3, Thomas JACQUET2 1STMicroelectronics, Crolles, Frances, 2APSYS-AIRBUS, France, 3Univ. Grenoble Alpes/CNRS/TIMA, FranceMonitoring and controlling handler temperature. Guy DECABOOTER Onsemi, Belgiu

ICS1 - Industry Case-Study Presentations Session 1

Strategies for Enabling Quantum Development with Test and Measurement at millikelvin range focusing on pre-characterization. Jack DEGRAVE1, Philip KRANTZ2, Dong-Thuc KNOBBE1 1FormFactor, USA, 2Keysight, USAChallenges and Solutions for Automotive Cold Test Elimination. Chen HE NXP Semiconductors, USARETE: DfRT, Test for Reliability & Data Analysis for zero defects and zero scraps. Mauro PIPPONZI, Alessandro MASERI, Luca MORICONI ELES Semiconductor Equipment, Italy3D interconnect Test Challenge. Sreejit CHAKRAVARTY Intel, US

A guided debugger-based fault injection methodology for assessing functional test programs

Functional test programs are increasingly used as flexible approaches to verify device functionality, both online (e.g., Software-Based Self Tests encapsulated in Software Test Library) and during the manufacturing test flow (e.g., System-Level Test). However, a traditional integrated development environment seldom analyzes functional test program weaknesses regarding fault-masking and propagation in CPU registers. Therefore, understanding the presence of errors in the programs due to logic faults at the end of the test program is only assessed by a signature computation, e.g., xor operation between all registers. The presence of program weaknesses in terms of data or control flow is not assessed, and it may lead to fault escapes and/or masking. In particular, those are perfect conditions for proliferating Silent data corruption and unrecoverable errors at the system level.This work aims to introduce a guided debugger-based fault injector framework to verify the fault propagation and masking capabilities of functional test programs by eventually catching program errors without relying on time-consuming simulation-based approaches. The fault-free instruction trace is dumped and analyzed to provide information about possible target registers of specific instructions for injecting faults, e.g., in jump instructions, where errors into registers may change the execution flow or not, to verify the presence of silent data corruptions and errors.The experimental results are carried out on an automotive device from the SPC58 family manufactured by STMicroelectronics, and faults are injected through a script running on Power Debug E40 from Lauterbach

Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults

Embedded nano-electronic devices have spread in daily life over the past ten years. Chip and embedded system manufacturing has thus become more challenging in recent years.When safety-critical sectors like the automobile are considered, addressing system anomalies and faults is crucial. Therefore, it is necessary to develop and research innovative ways to maintain high reliability in safety-critical sectors despite the complexity of present Systems-on-Chip (SoCs).In order to ensure high reliability, and be compliant with reliability standards, designers started to add additional circuitry to perform on-device tests. Built-In-Self-Test (BIST) is a technology that allows to conduct exhaustive tests within devices and, most importantly, without the need for external equipment. BIST can detect faults by outputting a signature at test end, which can be compared with a known value. Thus such known signatures are key, and in case of a signature mismatch it is not trivial to understand the root cause of the failure.This paper proposes a methodology to find the first failing pattern which causes the BIST’s signature to deviate and a way to collect good signatures from in-field devices, at key on/off, where BISTs are programmed and executed by the firmware at maximum frequency for an industrial case study produced by STMicroelectronics.The transition delay fault model is the primary target for the described work

On the integration and hardening of Software Test Libraries in Real-Time Operating Systems

The performance and complexity of Automotive System-on-Chip (SoC) have dramatically risen in the last decade thanks to technology scaling and moved to multicore capabilities. As a matter of fact, user requirements and the scenario complex-ity handled by devices are dramatically growing. Therefore, bare-metal safety-critical applications have shifted to a new application paradigm on top of Real-Time Operating Systems (RTOS). Safety standards require runtime self-check procedures the CPU executes from time to time. Such self-test procedures have strict requirements on their execution time and memory foot-print. The aforementioned self-test processes are also known as Software-Based Self Test encapsulated in Software Test Libraries. Following the shift to applications written on top of an RTOS, Software Test Libraries must also be integrated. This paper investigates possible software architectures when integrating Software Test Libraries in RTOSes with their pros e cons. Afterward, some hardening mechanisms are provided to overcome eventual problems in case permanent or transient faults arise. In order to simulate critical conditions, fault injections are performed via debugger in the Software Test Library to investigate their behavior and how they affect the system. Previously developed Software Test Library is integrated into a commercial RTOS called Micrium C OS-III. The fault injection campaign is performed on a real automotive System-on-Chip belonging to the SPC58 family from ST Microelectronics

Adaptive Management Techniques for Optimized Burn-In of Safety-Critical SoC

The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoC). This paper highlights problematic aspects of a Burn-In flow and describes a two-layered adaptive technique that permits to optimize the stress application and strongly reduce BI test time. At the SoC level, the described methodology adaptively copes with FLASH erase time uncertainties; at the Automatic Test Equipment (ATE) level, the strategy relies on power monitors and tester intelligence. The paper reports experimental results on a SoC manufactured by STMicroelectronics; figures show an optimized usage of stress resources and demonstrates a reduction of 25% of the BI test time when using the proposed adaptive techniques

An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip

The complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress.In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity.Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm