Parallel Multithread Analysis of Extremely Large Simulation Traces

With the explosion in the size of off-the-shelf integrated circuits and the advent of novel techniques related to failure modes, commercial Automatic Test Pattern Generator and fault simulation engines are often insufficient to measure the coverage of particular metrics. Consequently, a general working framework consists of storing simulation traces during the analysis phase and collecting test statistics from post-processing. Unfortunately, typical simulation traces can be hundreds of gigabytes long, and their analysis can require several days, even on large and powerful computational servers. In this paper, we propose a set of strategies to mitigate the evaluation time and the memory needed to analyze huge dump files stored in the standard Value Change Dump format. We concentrate on burn-in-related metrics that current commercial fault simulators and Automatic Test Pattern Generators cannot evaluate. We show how to divide the analysis process into several concurrent pipeline stages. We revise the logic process of each stage and all principal intermediate data structures, to adopt smart parallelization with very low contention and extremely low overhead. We exploit several low-level optimizations from modern programming techniques to reduce computation time and balance the different pipeline phases. We analyze simulation traces up to almost 250 GBytes computing different testing metrics. Overall, we can keep under control the memory usage, and we show time improvements of over two orders of magnitude compared to previously adopted state-of-the-art tools

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life

A Mathematical Model to assess the influence of parallelism in a Semiconductor Back-End Test Floor

The testing of IC at package level may require complex flows. In such cases, when the shop floor is fed with lots of multiple product lines, the manufacturing execution can suffer of very low efficiency, throughput limitation and longer cycle time than expected. The present work proposes a Mixed Integer Linear Programming model to evaluate the operational efficiency of the shop floor under different loading conditions and various shop floor characteristics. In particular, our computational campaign uses realistic data to evaluate the impact of increased parallelism and the effect of different parallelism distribution on the operational efficiency

System-in-package testing: problems and solutions

System in package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system on chip, which integrates multiple vendor parts. This article provides test strategies for known good die and known good substrate in the SiP. Case studies prove feasibility using the IEEE 1500 test structur