Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes

Abstract – Achieving the required time to market with economically acceptable yield levels and maintaining them in volume production has become a very challenging task in the most advanced technology nodes. One of the primary reasons is the relative increase in process variability in each generation. This paper will describe a comprehensive study of the main sources of variability and their effects on active devices, interconnect and ultimately product performance and yield. We will present benchmarking of yield loss components for different product classes. We will then propose several approaches for variability reduction in the design, yield ramp and volume manufacturing phases. EVOLUTION OF YIELD LOSS MECHANISMS In the older technology generations, manufacturing yield loss was dominated by random defects. By the time volum

A pattern recognition based method for IC failure analysis

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Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor

Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design

Fabrication based statistical design of monolithic IC's

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