Combining multi-valued logics in SAT-based ATPG for path delay faults

Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead to functional failures. Therefore, dynamic fault models like the Path Delay Fault Model (PDFM) have become more important in the last years. At the same time, classical algorithms for test pattern generation reach their limits due to the steadily increasing complexity of modern circuits. In this work, a SAT-based approach to calculate robust and non-robust test patterns for Path Delay Faults (PDF) is presented. In contrast to previous approaches, the sequential behavior of a circuit is modeled adequately. Moreover, tri-state elements and environment constraints that occur in industrial practice can be handled. The encoding to apply a Boolean SAT solver for this problem is motivated and explained in detail. Experimental results for large industrial circuits show the efficiency of this approach. 1

Restrict Encoding for Mixed–Mode BIST

Programmable mixed–mode BIST schemes combine pseudo–random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed–mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements. The scheme saves more than 50 % hardware costs compared with the best schemes known so far while complete programmability is still preserved

Experimental studies on SATbased ATPG for gate delay faults

The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits – where multi-valued logic has to be considered – is studied and experimental results are reported.

Studies on integrating SAT-based ATPG in an industrial environment

Due to ever increasing design sizes, more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently, SAT-based approaches for test pattern generation have been shown to be very efficient even on large industrial circuits. But these SAT-based techniques are not always superior to classical ATPG approaches. An integration of SAT-based engines into the classical ATPG flow can improve the overall performance. In this paper we present a first approach to integrate a SAT-based engine into the industrial ATPG environment of NXP Semiconductors. Experimental results for large industrial benchmark circuits are presented that show the improvements achieved by the integration