Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor

This paper evaluates N-detect scan ATPG patterns for their impact to test quality through simulation and fallout from production on a Pentium 4 processor using 90nm manufacturing technology. An incremental ATPG flow is used to generate N-detect test patterns. The generated patterns were applied in production with flows to determine overlap in fallout to different tests. The generated N-detect test patterns are then evaluated based on different metrics. The metrics include signal states, bridge fault coverage, stuck-at fault coverage and fault detection profile. The correlation between the different metrics is studied. Data from production fallout shows the effectiveness of N-detect tests. Further, the correlation between fallout data and the different metrics is analyzed. 1

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology

In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the “Primary Input (PI) pattern generation and simulation ” step and instead employs scan-dump values extracted from the tester. We utilize backward and forward logic implications of the scan-dump values to reconstruct more logic values for the circuit signals. Furthermore, we employ the reset state for the non-scan latches of the design to increase the number of specified signals in the overall circuit. Experimental results on stuck-at faults on industrial designs show that, in most cases, these reconstructed values are sufficient to correctly diagnose a fault, thereby avoiding hours of conventional functional diagnosis runtimes.