Survey on the Benefits of Using Memristors for Pufs

This paper reviews memristive PUFs (Physical Unclonable Functions) reported in the literature. The paper explains the motivation for using memristor technology for implementing PUFs. It focuses on PUFs’ applications, sizes, analysis, and physical variations. In addition, the paper presents the number of samples generated using Monte Carlo simulation for evaluating the PUF circuits. This paper also describes the protocols, functionality, and methodologies proposed in the memristive PUF literature. Although memristive PUFs are not commercialized yet, there is a high expectation of exploiting the memristors as fundamental elements in the next generation of hardware security primitives (e.g. PUF) due to their unique characteristics such as forming process, temporal drift, nonlinearity, bidirectionality, nonvolatility and model complexity. There have been some survey papers on memristor PUFs in the past, however, the field has continued to develop so a comprehensive survey including recent publications seemed in order at this time. Lately, memristor technology improvement has accelerated, therefore creating a need for an updated survey of the applications of memristors for PUFs

A 3D Crossbar Architecture for both Pipeline and Parallel Computations

A 3D architecture made up of a CMOS layer combined with a 3D stack of bipolar memristor crossbar arrays provides an innovative approach to hardware support for utilizing the strength of CMOS combined with the strength of memristors. Memristors have been evaluated for implementing a broad spectrum of applications such as memory, computations, hardware-based security primitives, cryptography, etc., and numerous studies have shown that memristors are desirable candidates for such applications. This paper proposes a novel 3D memristive crossbar architecture (i.e., a stack of memristive crossbar arrays built on top of CMOS substrate) with a specific focus on the way of connecting the crossbar arrays to the CMOS layer. The proposed architecture is configurable and allows restructuring crossbar arrays and creating 1D arrays with adjustable sizes. The proposed architecture enables parallel and pipeline computations where data can move or be processed in planes perpendicular to the stacked crossbar arrays. In addition, the proposed architecture is scalable meaning that stacks of crossbar arrays can be connected without additional overhead. This paper shows examples of implementing a full adder, a 4-bit look-ahead carry generator, and an 8-bit multiplexer. Simulations and area, delay, and power analysis demonstrate the behavior of the proposed 3D circuit

Multi-input Volistor Logic XNOR Gates

A novel approach utilising the emerging memristor technology is introduced for realising a 2-input primitive XNOR gate. This gate enables in-memory computing and is used as a building block of multi-input XNOR gates. The XNOR gate is realised with eight memristors of two crossbar arrays. The average power consumption of an 8-input XNOR gate is calculated and compared with its counterpart realised with CMOS technology – the XNOR gate consumes less power. ESOP realisation can be directly implemented with XNOR gates. Our simulation results and comparisons show the benefit of the proposed XNOR gate in terms of delay, area, and power. Volistor logic XNOR gate. (a) Circuit diagram of two-input volistor logic XNOR gate. Input voltages are applied to memristors S1 and S2 through horizontal wires Win1 and Win2, and the output which is logical AND of states S1 and S2 is calculated by applying VREAD to vertical wire WXNOR. (b) Block diagram of two-input volistor logic gate. (c) A multi-input volistor logic XNOR gate can be implemented by connecting two XNOR gates though CMOS switches