Testing The Effective Performance Of Ofdm On Digital Video Broadcasting

One of the most exciting areas in telecommunications and networking is wireless technology. The rapid growth of mobile telephone uses various satellite services. So, the present work deals with high data stream applications of Digital Video Broadcasting (DVB), which takes an important place in the studies and development researches due to its direct contacts on the human daily life. In this design the focusing is on the modern types of DVB where modified module of the Terrestrial DVB for Handheld terminals (DVB-H) is used and it was simulated to perform the physical layer of the designed system. Different modes of DVB-H with high bit rate of Orthogonal Frequency Division multiplexing (OFDM) and high number of sub-carriers are considered to show the effect of Coded Orthogonal Frequency Division multiplexing (COFDM) on the system SNR using the convolutional encoding. The modes are tested to show the characteristics of each type involving BER calculation. The obtained results show the effect of OFDM in the designed system by evaluating it using AWGN and mobile multipath channels. These demonstrate the effective of OFDM over single carrier systems where the complexity and cost of implementation are both increaseed by increasing number of carrier. The elimination of ISI is achieved using efficient coding techniques with small guard time. The 4k mode shows good performance in mobile reception, providing satisfactory and reasonable receiver cost/complexity. The Peak Signal to Noise Ratio (PSNR) measurement of the reconstructed received image pixels provides more mentality and good comparing method than the BER measuring. The obtained results are compared between the PSNR of each reconstructed images for different modes with the corresponding transmitting SN

Design And Implementation Of High Speed Complex Multiplier Using Fpga

Multiplication is an important part in real-time digital signal processing (DSP). The present work deals with the design and implement of complex  ultiplier/mixer using Field Programmable Gate Array (FPGA) chip with low cost and high speed. Two devices of FPGA are chosen to implement the design; to achieve the task of mixer system implementation. The rules that are important for such implementation are proposed in order to reach the minimum cost and high speed requirement for the individual component of mixer system. These components are software simulated using VHDL language, with software called MODELSIM version SE-EE5.4a. Since mixer is important in any digital receiver because of high speed need, so different multiplier method are proposed with different data resolution and different worst case of additional noise. To achieve high speed data, a parallel tree multiplier is used with Wallace tree method which is optimal in speed but it has a complicated routing that makes it impractical to implement, because of this, we present a modification for fast parallel multiplier using both Wallace tree and Booth algorithm to achieve a sufficient design for most of DSP application. The proposed design of mixer is simulated using ISE4.1i and results in successful achievement of its desired specification. The final implementation of programmable (4, 8, 16, 32 and 64) bit mixer data input resolution is achieved using Virtex-II devices and also implemented in LP-2900 CPLD device. The resulting performance depending on multiplier method are viewed in mixer cost. However, the routing is much more regular with great reduction in FPGA cost and it is achieved for the desired mixer when compared with other methods