Design of a high speed and low latency crypto-processor ASIC

This paper presents the design of an ultra high speed crypto-processor for next generation IT security. It addresses the next generation IT security requirements: the resistance against all attacks and high speed with low latency. The proposed processor is capable of generating cryptographically secured information at a rate of multi-ten Gbps. The performance of the processor is compared with that of other researchers which proves it's superiority over them

Design of a testchip for low cost IC testing.

With the continuous increase of the integration densities and complexities, the problem of testing integrated circuits has become much more acute and needs an economic solution with reliable performance. This paper presents the design of a TESTCHIP implementing a multiple polynomial, multiple seed based mixed-mode test technique. Fault simulation experiments on benchmark circuits show that the TESTCHIP is capable of detecting 100% of the faults using a much lower number of test vectors than in the approaches attempted by the other researchers. It also offers lower data storage requirements than that of conventional ATE. The TESTCHIP is capable of testing combinational circuits as well as sequential circuits with scan-path facilities

Radiation measurement from mobile base stations at a university campus in Malaysia

The tremendous growth of telecommunication industry results the number of hand phone users increases everyday. In order to support the growing number of users, the mobile base stations can be seen in almost everywhere. This scenario has created uncomfortable feelings to the people that they may be affected by the radiations from antennas. A measurement was done at student hostels and office premises near to base stations in International Islamic University Malaysia, Gombak campus. Measured values are compared with Malaysian Communication and Multimedia Commission (MCMC), IEEE and ANSI recommendations for safety guidelines. The results are presented in this study

Design of an Ultra High Speed AES Processor for Next Generation IT Security.

The Advanced Encryption Standard (AES) has added new dimension to cryptography with its potentials of safeguarding the IT systems. This paper presents the design of an ultra high speed AES processor to generate cryptographically secured information at a rate of multi-ten Gbps. The proposed design addresses the next generation IT security requirements: the resistance against all crypto-analytical attacks and high speed with low latency. This work optimizes AES algorithm to eliminate algebraic operations from the datapath, which contributes to achieve ultra high speed and to reduce the latency. The AES processor is designed using Verilog HDL and then simulated using FPGA platform. The performance of the processor is compared with that of other researchers in terms of speed and latency, which shows its superiority over them. The soft core can be reused to convert it to ASIC to achieve much better performance

RC4A stream cipher for WLAN security: a hardware approach

Wireless networks are on the cutting edge of modern technology and rapidly gaining popularity in today’s world due to their excellent usability. For secure wireless data transmission, Wired Equivalent Privacy (WEP), IEEE 802.11 standard defined security protocol, is employed. WEP has a potential limitation that stems from its adaptation of RC4 stream cipher algorithm. As a result, there is a pressing need for new WLAN security measure. Therefore, this paper presents hardware implementation of RC4A stream cipher and proposes to replace RC4 in WLAN security scheme, due to weakness of RC4.The design of the cipher was implemented by Verilog HDL. For hardware implementation of the design, an Altera Field Programmable Gate Array (FPGA) device, EP20K200EFC484-2X from APEX family, APEX 20KE, was used

Discovering decision algorithm from a distance relay event report

In this study rough-set-based data mining strategy was formulated to discover distance relay decision algorithm from its resident event report. This derived algorithm, aptly known as relay CD-prediction rules, can later be used as a knowledge base in support of a protection system analysis expert system to predict, validate or even diagnose future unknown relay events. Nowadays protection engineers are suffering from very complex implementations of protection system analysis due to massive quantities of data coming from diverse points of intelligent electronic devices. In helping the protection engineers deal with this overwhelming data, this study relied merely on digital protective relay’s recorded event report because, among other intelligent electronic devices, digital protective relay sufficiently provided virtually most attributes needed for data mining process in knowledge discovery in database. The method of discovering the distance relay decision algorithm essentially involved formulating rough set discernibility matrix and function from relay event report, finding reducts of pertinent attributes using genetic algorithm and finally generating relay prediction rules. The classification accuracy and the area under the ROC curve measurements provided an acceptable evaluation of the fact that the discovered relay decision algorithm

Knowledge discovery in distance relay event report: a comparative data-mining strategy of rough set theory with decision tree

A protective relay performance analysis is only feasible when the hypothesis of expected relay operation characteristics as decision rules is established as the knowledge base. This has been meticulously accomplished by soliciting the relay knowledge domain from protection experts who are usually constrained by their experience and expertise. Manually analyzing an event report is also cumbersome due to the tremendous amount of data to be perused. This paper addresses these issues by intelligently divulging the knowledge hidden in the relay recorded event report using a data-mining strategy based on rough set theory and a rule-quality measure under supervised learning to discover the relay decision algorithm and association rule. The high prediction accuracy rate and the close-to-unity areas under ROC curve value of the relay operating characteristic curve of the discovered relay decision algorithm verifies its generalized ability to predict trip status in an expert system of relay performance analysis. The relay association rule that was subsequently discovered by using the rule-quality analysis had also been verified as being a reliable hypothesis of the relay operation characteristics. This hypothesis helps the protection engineers understand the behavior of the distance relay. These rules would then be compared with and validated by benchmarking decision-tree-based data-mining analysis

Making implicit knowledge of distance protective relay operations and fault characteristics explicit via rough set based discernibility relationship

This paper discusses the novel application of the discernibility concept inherent in rough set theory in making explicit of the implicit knowledge of distance protective relay operations and fault characteristics that are hidden away in the recorded relay event report. A rough-set-based data mining strategy is formulated to analyze the relay trip assertion, impedance element activation, and fault characteristics of distance relay decision system. Using rough set theory, the uncertainty and vagueness in the relay event report can be resolved using the concepts of discernibility, elementary sets and set approximations. Nowadays protection engineers are suffering from very complex implementations of protection system analysis due to massive quantities of data coming from diverse points of intelligent electronic devices (IEDs such as digital protective relays, digital fault recorders, SCADA's remote terminal units, sequence of event recorders, circuit breakers, fault locators and IEDs specially used for variety of monitoring and control applications). To help the protection engineers come to term with the crucial necessity and benefit of protection system analysis without the arduous dealing of overwhelming data, using recorded data resident in digital protective relays alone in an automated approach called knowledge discovery in database (KDD) is certainly of an immense help in their protection operation analysis tasks. Digital protective relay, instead of a host of other intelligent electronic devices, is the only device for analysis in this work because it sufficiently provides virtually most attributes needed for data mining process in KDD. Unlike some artificial intelligence aproaches like artificial nueral network and decision tree in which the data mining analysis is "population-based" and single since it is common to the entire population of training data set, the rough set approach adopts an "individually-event-based" paradigm in which detailed time tracking analysis of relay operation has been successfully performed

Development of a Functional Digital Integrated Circuit Testing System Using Mixed-Mode Technique

With the continuous increase in design complexities and packing densities of integrated circuit (IC), problems associated with conventional Automatic Test Equipment (ATE)-based IC testing approach have become a burning issue in the semiconductor world, which needs an economic solution with reliable performance. Recently, the superiority of Dynamic Reseeding-based Mixed-mode (DRM) technique has been proven over all other existing test techniques in the Built-in Self-Test (BIST) environment. This thesis introduces the implementation of the DRM technique in a system-on-a-chip (SOC) in alleviating the problems of conventional ATE-based external testing of digital IC. The performance of the SOC in IC testing has been verified using fault simulation experiments on the ISCAS85 benchmark circuits (Circuits proposed in the International Symposium on Circuits and Systems in 1985). Significant improvement is observed in achieving complete fault coverage for the ISCAS85 benchmark circuits using acceptable number of test vectors. Fault simulation results show that the proposed DRM technique produces 100% fault coverage for the benchmark circuits c432, c1355, c1908, c2670, c3540 and c5315 using the 232, 526, 996, 336, 360 and 748 test cubes, respectively which are much lower than the numbers from the approaches suggested by other researchers. It also offers much lower data storage requirements in IC testing than the conventional ATE-based testing approach. The results show that 2 to 11 times less memory is needed for testing the ISCAS85 benchmark circuits using the DRM technique than that of the deterministic testing approach. Verilog Hardware Description Language (HDL), which is an industry standard IC design tool, has been used to design the SOC proposed in this thesis. Main modules of the SOC are micro-UART (Universal Asynchronous Receiver and Transmitter), a controller, pattern generator, signature analyzer (SA), instruction registers and Random Access Memories (RAMs). A prototype test set-up has been developed for testing IC by implementing the design of the SOC into a Field Programmable Gate Array Logic (FPGA) chip and then by interfacing the FPGA chip with a personal computer (PC) through a Graphical User Interface (GUI). For testing a circuit, necessary test information is loaded into the SOC and the testing process is executed using the GUI from the PC. The SOC goes into autonomous mode. It generates test vectors, applies them to the Circuit Under Test (CUT) and captures the output responses and sends it into the SA for compression. At the end of testing, the generated signature is compared with that of a reference circuit (fault-free circuit of the same type) and the CUT is identified as fault-free if the two signatures are the same and as faulty if otherwise. The operation of the SOC has been verified in real time by testing a 16-bit multiplier as a sample CUT. It is user programmable, which increases flexibility and reliability in IC testing. It is capable of testing functionality of combinational circuits as well as sequential circuits with scan-path facility