Impact of NoFPGA IP router architecture on link bandwidth

In today\u27s world of advanced technology numerous applications are computationally intensive. This created an opportunity for the development of new System-on-Chip (SoC) design techniques to allow easy IP cores (Intellectual Property cores) re-use and integration under time-to-market pressure. A wide range of these newly emerging design platforms is now drifting towards highly integrated System-on-Chip designs with many on-chip processing resources like processors, DSPs, and memories. Using this technique, designers can build System-on-Chip (SoC) by integrating dozens of IP cores. As the number of IP cores integrated on a chip increases, the on-chip communication and physical interconnections become a bottleneck. New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. New communication architecture, the NoFPGA (Network-on-FPGA), for future SoFPGA (System-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoFGPA design methodology built in a single FPGA device are addressed. Mainly, the performance analysis of the IPRouter of both Torus and Mesh topologies is addressed. © 2008 IEEE

Impact of buffering mechanism on SoFPGA ip router cost

In today\u27s world of advanced technology numerous applications are computational intensive. This created an opportunity for the development of new System-on-Chip (SoC) design techniques to allow easy IP cores (Intellectual Property cores) re-use and integration under time-to-market pressure. New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. New communication architecture, the NoFPGA, for future SoFPGA has been presented. The IP router is the heart of NoFPGA. The design cost of IPRouter Buffering, the most expensive building block, is evaluated based on two different implementation approaches. First, IPRouter buffering based on distributed memory. Second, IPRouter buffering based on Embedded Block RAMs. © 2006 IEEE

Performance analysis of future system-on-FPGA topology candidates

New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. The currently used Bus-Centered approach becomes an inappropriate choice because of its limitation as a shared medium that restricts the scalability of the communication architecture. Also, long bus wires result in performance degradation due to the increased capacitive load. The long wires also consume more power to drive all of Intellectual Property Cores, IP Cores, on the bus. New communication architecture, the NoFPGA (Network-on-FPGA), for future SoFPGA (System-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoC design methodology built in a single FPGA device are addressed. Mainly, the problem of achieving efficient NoFPGA performance through investigating the best topology is addressed. Results of the work show that the 2D Torus NoFPGA outperforms the 2D Mesh NoFPGA. On the other hand, Power estimate analysis showed that the Mesh NoFPGA represents a 30% power drop compared to the equivalent Torus NoFPGA which makes the Mesh NoFPGA is a better candidate for power critical application. © 2009 IEEE