Design of a smart power manager for digital communication systems

Portable devices, like mobile phones, are in an increasing need for power due to the growing complexity of applications and services provided by them. At the same time, mobile devices need to adapt their communication techniques so as to be able to work with different communication standards. The need for a multistandard communication circuit arises to overcome such a problem. Unfortunately, these circuits need to consume a considerable amount of power to achieve their designed goal. The researchers use the Dynamic Voltage / Frequency Scheduling technique to reduce power consumption in digital systems. This method employs the task time to schedule the system supply voltage along the task time to reduce the overall consumed power. Since the task time in digital communication systems is not defined, the application of the dynamic voltage/frequency technique on such systems is not possible. In this research, a closer look at the digital circuit power dissipation is given. Then, a new power model is introduced which can predict the digital circuit instantaneous power dissipation accurately. This model is used to build a power control strategy that makes use of the frequency as a control parameter. A setup is carried out using MATLAB to simulate the power of a NOT gate, a multiplexer circuit, a full adder and a two-bit full adder. The results are compared with OrCAD Cadence simulation for the same circuits. The results show that the new model can simulate the power dissipation accurately under different voltages, frequencies, and different technology sizes. In the second part of this research, a smart power manager is designed based on a fuzzy logic controller. The smart power manager makes use of the measured power and the input frequency to produce the required voltage to the digital system. The smart power manager is tested on a multiplexer circuit, two-bit full adder circuit, and cyclic redundancy check circuits. The results of the simulations show that the manager can reduce up to 60% of the consumed power by these circuits in low frequencies and up to 5% of the consumed power in high frequencies. The smart power manager can fulfil the purpose of the dynamic voltage/frequency scheduling technique without the need for the task time. In the final part of this research, the Long Term Evolution (LTE) system is taken as a case study. A unique cyclic redundancy check circuit is designed. This circuit is directed to work with LTE systems, so it has three generators integrated into it. The circuit can select the needed cyclic redundancy generator and produce the required remainder for the LTE system. The smart power manager is modified to supply both the voltage and frequency to the new cyclic redundancy check circuit so that it can control its consumed power. The selection of frequency depends on the used cyclic redundancy generator and the used modulation technique. The selected frequency ensures that the data rate between the LTE stages is constant. The results of the setup show that the smart power manager is capable of reducing the power of the circuit by more than 40% if it was operating at a constant frequency. The smart power manager can lower the power of the cyclic redundancy check circuit by more than 20% if the circuit is running under variable clock frequency. The conclusion driven from the results above proves that the SPM can reduce the consumed power in multi standard systems and Software Defined Radio (SDR) circuits

SPARC 2017 retrospect & prospects : Salford postgraduate annual research conference book of abstracts

Welcome to the Book of Abstracts for the 2017 SPARC conference. This year we not only celebrate the work of our PGRs but also the 50th anniversary of Salford as a University, which makes this year’s conference extra special. Once again we have received a tremendous contribution from our postgraduate research community; with over 130 presenters, the conference truly showcases a vibrant PGR community at Salford. These abstracts provide a taster of the research strengths of their works, and provide delegates with a reference point for networking and initiating critical debate. With such wide-ranging topics being showcased, we encourage you to exploit this great opportunity to engage with researchers working in different subject areas to your own. To meet global challenges, high impact research inevitably requires interdisciplinary collaboration. This is recognised by all major research funders. Therefore engaging with the work of others and forging collaborations across subject areas is an essential skill for the next generation of researchers

A multi polynomial CRC circuit for LTE-Advanced communication standard

Long Term Evolution Advanced (LTE-A) uses four different kinds of Cyclic Redundancy Check (CRC) to verify the integrity of the transmitted data, which implies using four circuits for each CRC in the transceiver system. In this paper, a novel algorithm is introduced to combine three of these CRC circuits into one in order to minimize the total area of the transceiver. This method will insure a considerable reduction in the dynamic power of the system. The new circuit is designed in a parallel fashion and is tested on an Altera FPGA platform to verify its power consumption and number of used gates hence, the total reduction in size. The result shows a good reduction in the number of used logic gates