Tectonic and geologic evolution of Syria

Publisher's version archived with permission from publisher.Using extensive surface and subsurface data, we have synthesized the Phanerozoic tectonic and geologic evolution of Syria that has important implications for eastern Mediterranean tectonic studies and the strategies for hydrocarbon exploration. Syrian tectonic deformation is focused in four major zones that have been repeatedly reactivated throughout the Phanerozoic in response to movement on nearby plate boundaries. They are the Palmyride Mountains, the Euphrates Fault System, the Abd el Aziz-Sinjar uplifts, and the Dead Sea Fault System. The Palmyrides include the SW Palmyride fold and thrust belt and two inverted sub-basins that are now the Bilas and Bishri blocks. The Euphrates Fault System and Abd el Aziz-Sinjar grabens in eastern Syria are large extensional features with a more recent history of Neogene compression and partial inversion. The Dead Sea transform plate boundary cuts through western Syria and has associated pull-apart basins. The geological history of Syria has been reconstructed by combining the interpreted geologic history of these zones with tectonic and lithostratigraphic analyses from the remainder of the country. Specific deformation episodes were penecontemporaneous with regional-scale plate-tectonic events. Following a relatively quiescent early Paleozoic shelf environment, the NE-trending Palmyride/Sinjar Trough formed across central Syria in response to regional compression followed by Permian-Triassic opening of the Neo-Tethys Ocean and the eastern Mediterranean. This continued with carbonate deposition in the Mesozoic. Late Cretaceous tectonism was dominated by extension in the Euphrates Fault System and Abd el Aziz-Sinjar Graben in eastern Syria associated with the closing of the Neo-Tethys. Repeated collisions along the northern Arabian margin from the Late Cretaceous to the Late Miocene caused platform-wide compression. This led to the structural inversion and horizontal shortening of the Palmyride Trough and Abd el Aziz-Sinjar Graben

ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING

ABSTRACT In this paper we, present a new heuristic called PowerFM which is a modification of the well-known Fidducia Mattheyeses algorithm for VLSI netlist partitioning. PowerFM considers the minimization of power consumption due to the nets cut. The advantages of using PowerFM as an initial solution generator for other iterative algorithms, in panicular Genetic Algorithm (GA) and Tabu Search (TS), for multiobjective optimization is investigated. A series of experiments are conducted on ISCAS-85/89 benchmark circuits to evaluate the efficiency of the PawerFM algorithm. Results suggest that this heuristic would provide a good starting solution for multiobjective optimization using iterative algorithms

An efficient test relaxation technique for combinational circuits based on critical path tracing

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude

An efficient test relaxation technique for combinational & full-scan sequential circuits

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated

An efficient test relaxation technique for synchronous sequential circuits

Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set

On efficient extraction of partially specified test sets for synchronous sequential circuits

Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences, i.e. extracting partially specified test sequences, can improve the efficiency of both test compression and test compaction. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set

An efficient test relaxation technique for combinational circuits based on critical path tracing

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude