Nanostructures Technology, Research, and Applications

Contains reports on twenty-four research projects and a list of publications.Joint Services Electronics Program Grant DAAHO4-95-1-0038Defense Advanced Research Projects Agency/Semiconductor Research Corporation SA1645-25508PGU.S. Army Research Office Grant DAAHO4-95-1-0564Defense Advanced Research Projects Agency/U.S. Navy - Naval Air Systems Command Contract N00019-95-K-0131Suss Advanced Lithography P. O. 51668National Aeronautics and Space Administration Contract NAS8-38249National Aeronautics and Space Administration Grant NAGW-2003Defense Advanced Research Projects Agency/U.S. Army Research Office Grant DAAHO4-951-05643M CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research Contract N66001-97-1-8909National Science Foundation Graduate FellowshipU.S. Army Research Office Contract DAAHO4-94-G-0377National Science Foundation Contract DMR-940034National Science Foundation Grant DMR 94-00334Defense Advanced Research Projects Agency/U.S. Air Force - Office of Scientific Research Contract F49620-96-1-0126Harvard-Smithsonian Astrophysical Observatory Contract SV630304National Aeronautics and Space Administration Grant NAG5-5105Los Alamos National Laboratory Contract E57800017-9GSouthwest Research Institute Contract 83832MIT Lincoln Laboratory Advanced Concepts ProgramMIT Lincoln Laboratory Contract BX-655

Nanofabrication of arrays of silicon field emitters with vertical silicon nanowire current limiters and self-aligned gates

We developed a fabrication process for embedding a dense array (10⁸cm⁻²) of high-aspect-ratio silicon nanowires (200 nm diameter and 10 μm tall) in a dielectric matrix and then structured/exposed the tips of the nanowires to form self-aligned gate field emitter arrays using chemical mechanical polishing (CMP). Using this structure, we demonstrated a high current density (100 A cm⁻²), uniform, and long lifetime (>100 h) silicon field emitter array architecture in which the current emitted by each tip is regulated by the silicon nanowire current limiter connected in series with the tip. Using the current voltage characteristics and with the aid of numerical device models, we estimated the tip radius of our field emission arrays to be ≈4.8 nm, as consistent with the tip radius measured using a scanning electron microscope (SEM).United States. Space and Naval Warfare Systems Command (N66001-12-1-4212)United States. Space and Naval Warfare Systems Command (N66001-15-1-4022

Electron transmission through suspended graphene membranes measured with a low-voltage gated Si field emitter array

We experimentally demonstrate the transmission of electrons through different number (1, 2, and 5) of suspended graphene layers at electron energies between 20 and 250 eV. Electrons with initial energies lower than 40 eV are generated using silicon field emitter arrays with 1 μm pitch, and accelerated towards the graphene layers supported by a silicon nitride grid biased at voltages from −20 to 200 V. We measured significant increase in current collected at the anode with the presence of graphene, which is attributed to the possible generation of secondary electrons by primary electrons impinging on the graphene membrane. Highest output current was recorded with monolayer graphene at approximately 90 eV, with up to 1.7 times the incident current. The transparency of graphene to low-energy electrons and its impermeability to gas molecules could enable low-voltage field emission electron sources, which often require ultra-high vacuum, to operate in a relatively poor vacuum environment.AFOSR/MURI (Contract FA9550-18-1-0436)DARPA (Contract N66001-16-1-4038

Scanning anode field emission microscopy of a single Si emitter

Emitter tip radius nonuniformity results in exponential variations in emission current and a relatively low array utilization. Here, we provide a method of mapping the current and field-factor from a single emitter over a small area using a scanning anode field emission microscope. A dull W probe is used as the anode, and an array of emitters is fabricated on silicon (Si) wafers. We use a relatively wide spaced (100 [Formula: see text]m pitch) emitter array with each emitter having an integrated Si pillar. Current-voltage characteristics are used to extract the field-factor and to experimentally demonstrate the mapping of the currents and field-factor of a single emitter. From emission spot sizes, the emission half-angles are measured to be [Formula: see text] at anode voltages 2.5 kV and a minimum resolvable feature of 2–3 [Formula: see text]m at 1.8 kV. We also determine the field-factor dependence with the distance between the anode and the emitter, where limiting the current becomes essential to prevent early burn-out of the emitter that could reduce the current. We also simulated the maximum currents tolerated by the pillar to assess the thermal effects on the emitter. Finite element modeling confirms the experimental trend in the field-factor with the distance between the anode and the emitter tip, resulting in a value of approximately [Formula: see text] cm[Formula: see text] for an emitter tip radius of 5 nm and an emitter-anode distance of 50 [Formula: see text]m. </jats:p

The globalization of R&D's implications for technological capabilities in MNC home countries: Semiconductor design offshoring to China and India

This paper addresses the empirical question of the impact of the offshoring of semiconductor design to India and China on the generation of semiconductor design skills in the offshoring multinational corporations' (MNCs) home countries. There are four main findings. First, there is a specific technology skill ladder for training “design leads” or design managers within this industry that entails direct exposure to a wide range of design activities. Thus, offshoring has potentially serious implications for development of further design leads. Second, the paper also finds that the impact on skills activities and thus potential skills generation at home from offshoring to India has been limited and gradual and from offshoring to China has been even more limited although the activities done in each country by MNCs have risen over time. Third, the fuzzy set qualitative comparative analysis pinpoints that the operations with design leads and large design teams in 2003–2007 in conjunction with other attributes are generally the ones that pursued the most extensive expansion of semiconductor design offshoring during the subsequent 2009–2013 period. Finally, the evidence for a gradual process of offshoring from the second and third points suggests that offshoring in semiconductor design will most likely not displace the large amount of design activities in the home countries of the MNCs in the near future

Nanofabricated Low-Voltage Gated Si Field-Ionization Arrays

We demonstrate high-density (1-μm pitch) silicon field-ionization arrays (FIAs) with self-aligned gate apertures (350 nm in diameter) and integrated nanowire current regulators. Our FIAs achieved high field factors (>0.1 nm⁻¹) and significantly lower ionization voltages (<100 V) than the devices with lower tip densities previously reported. Ion currents were measured in argon, deuterium, and helium at pressures from 1 to 16 mTorr. The FIAs turned on between 70 and 85 V, and the ion currents of around 0.4 nA were measured at 100 V. Higher currents of 7 nA were obtained at 147 V and 16 mTorr, but with the risk of gate damage by the ions energized in the intense gate-ionizer field. Si FIAs coated with Pt resulted in higher field factors due to sharper tips, but lower ion currents. Surface states, coupled with molecular adsorption and transport to the ionizer, are the possible mechanisms for lower voltage ionization in the uncoated Si FIAs

Gated Silicon Field Emitter Array Characterization

Arrays of silicon (Si) field emitter tips are being studied for use as electron source for vacuum nano-transistors. These arrays are analyzed using the CST particle tracking solver and via experiment. Simulations are used to study the potential transfer characteristics and performance for use as transistors for the vertical emitter structures. An experimental system has been developed to test the arrays under high temperature (400° C) and for various gases to study the noise characteristics and the effects of adsorption and desorption on performance