High-Throughput and Improved-Convergent Design of Pipelined Adaptive DFE for 5G Communication

This brief presents a high-throughput and improved convergent design of pipelined adaptive decision feedback equalizer (ADFE) for 5G communication system. The proposed ADFE design achieves 3.3 Gbps for 4-quadrature amplitude modulation (4-QAM) and 8th order feedback filter (FBF). A novel look-up table update scheme for M-ary QAM ADFE is proposed. Further, we present an efficient quantization scheme for the proposed design. Theoretical derivations and simulation results confirm that the convergence performance of the proposed ADFE is superior. For instance, the proposed design for 16-QAM and 16th order FBF takes 167 less iterations and improves 4.03 dB error performance, while it provides nearly 8.96 times higher throughput as compared to the best existing design

High-Performance VLSI Architecture of DLMS Adaptive Filter for Fast-Convergence and Low-MSE

This brief presents a high-performance VLSI architecture of delayed least mean square (DLMS) adaptive filter for fast-convergence and low-mean square error (MSE) using distributed arithmetic (DA). The proposed design estimates response against the adaptation delays using a parallel predictive adder tree followed by a shift accumulate (SA) unit. An efficient quantization scheme with two bits of scaled error signal is also suggested. Single SA unit for multiple DA bases is used to reduce the number of adders and registers. Simulation and synthesis results show that the proposed design for 32nd order provides 19.72% lesser area, 25.51% lesser power, lesser 28.89% MSE and 59.91% lesser MSE/area over the best existing design.</p

An Efficient Scheme for Acoustic Echo Canceller Implementation Using Offset Binary Coding

This article presents an efficient design and implementation scheme for a low-area and low-power acoustic echo canceller. The design employs the block least mean square algorithm-based adaptive filter (ADF) using offset binary coding. The proposed approach first formulates the ADF by splitting the matrix–vector multiplication into smaller ones. Each of them is then realized with lookup tables and shift accumulate units with offset terms. An efficient scheme is suggested to update the offset terms from the corresponding lookup tables. In addition, a novel optimization scheme is proposed based on the grouping of partial products (PPs) and moving windows. The PPs are generated in two parallel styles using adders, multiplexers, and registers. The optimized architecture is shared to compute both the filter output and coefficient increment terms in every iteration. The fixed-point quantization model for the architecture is also discussed. Accuracy measure is defined to characterize the proposed design and compare it with the Cramer–Rao lower bound. Simulations are carried out to evaluate the performance of the proposed design. Field-programmable gate array implementation results and application-specific integrated circuit synthesis show that the proposed design outperforms the state-of-the-art architectures

Partial-LUT Designs for Low-Complexity Realization of DA-Based BLMS Adaptive Filter

This brief presents two-optimized partial look-up table (LUT) designs for low-complexity realization of distributed arithmetic (DA) based block least-mean-square (BLMS) adaptive filter (ADF). These are based on the partial add-store (PAS) and partial store-add (PSA) methods. A novel optimization scheme is presented which exploits the redundancies between the partial inner-products with sliding-window of input-block. It is found that the PAS method provides shorter critical-path-delay than the PSA method. A case study on echo-cancellation is demonstrated for architectural trade-off between the proposed designs. Synthesis results show that the proposed PSA based BLMS ADF for 64th order offers 41.04% lesser area and 39.38% lesser power, while the PAS based BLMS ADF provides 52.08% lesser area and 50.05% lesser power as compared to the best existing work