Nonlinear control of two-stage single-phase standalone photovoltaic system

This paper presents a single-phase Photovoltaic (PV) inverter with its superior and robust control in a standalone mode. Initially, modeling and layout of the Buck-Boost DC-DC converter by adopting a non-linear Robust Integral Back-stepping controller (RIBSC) is provided. The controller makes use of a reference voltage generated through the regression plane so that the operating point corresponding to the maximum power point (MPP) could be achieved through the converter under changing climatic conditions. The other main purpose of the Buck-Boost converter is to act like a transformer and produce an increased voltage at the inverter input whenever desired. By not using a transformer makes the circuit size more compact and cost-effective. The proposed RIBSC is applied to an H-bridge inverter with an LC filter to produce the sinusoidal wave in the presence of variations in the output to minimize the difference between the output voltage and the reference voltage. Lyapunov stability criterion has been used to verify the stability and finite-time convergence of the overall system. The overall system is simulated in MATLAB/Simulink to test the system performance with different loads, varying climatic conditions and inverter reference voltages. The proposed methodology is compared with a back-stepping controller and Proportional Integral Derivative (PID) controller under rapidly varying climatic conditions. Results demonstrated that the proposed technique yielded a tracking time of 0.01s, a total harmonic distortion of 9.71% and a root means square error of 0.3998 in the case of resistive load thus showing superior control performance compared to the state-of-the-art control techniques

Passivity-based Rieman Liouville fractional order sliding mode control of three phase inverter in a grid-connected photovoltaic system

Photovoltaic (PV) system parameters are always non-linear due to variable environmental conditions. The Maximum power point tracking (MPPT) is difficult under multiple uncertainties, disruptions and the occurrence of time-varying stochastic conditions. Therefore, Passivity based Fractional order Sliding-Mode controller (PBSMC) is proposed to examine and develop a storage function in error tracking for PV power and direct voltage in this research work. A unique sliding surface for Fractional Order Sliding Mode Control (FOSMC) framework is proposed and its stability and finite time convergence is proved by implementing Lyapunov stability method. An additional input of sliding mode control (SMC) is also added to a passive system to boost the controller performance by removing the rapid uncertainties and disturbances. Therefore, PBSMC, along with globally consistent control efficiency under varying operating conditions is implemented with enhanced system damping and substantial robustness. The novelty of the proposed technique lies in a unique sliding surface for FOSMC framework based on Riemann Liouville (R-L) fractional calculus. Results have shown that the proposed control technique reduces the tracking error in PV output power, under variable irradiance conditions, by 81%, compared to fractional order proportional integral derivative (FOPID) controller. It is reduced by 39%, when compared to passivity based control (PBC) and 28%, when compared to passivity based FOPID (EPBFOPID). The proposed technique led to the least total harmonic distortion in the grid side voltage and current. The tracking time of PV output power is 0.025 seconds in PBSMC under varying solar irradiance, however FOPID, PBC, EPBFOPID, have failed to converge fully. Similarly the dc link voltage has tracked the reference voltage in 0.05 seconds however the rest of the methods either could not converge, or converged after significant amount of time. During solar irradiance and temperature change, the photovoltaic output power has converged in 0.018 seconds using PBSMC, however remaining methods failed to converge or track fully and the dc link voltage has minimum tracking error due to PBSMC as compared to the other methods. Furthermore, the photovoltaic output power converges to the reference power in 0.1 seconds in power grid voltage drop, whereas other methods failed to converge fully. In addition power is also injected from the PV inverter into the grid at unity power factor

Software and hardware techniques for accelerating MPEG2 motion estimation

EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Global Maximum Power Point Tracking of Partially Shaded PV System Using Advanced Optimization Techniques

In this work, a meta-heuristic optimization based method, known as the Firefly Algorithm (FA), to achieve the maximum power point (MPP) of a solar photo-voltaic (PV) system under partial shading conditions (PSC) is investigated. The Firefly Algorithm outperforms other techniques, such as the Perturb & Observe (P&O) method, proportional integral derivative (PID, and particle swarm optimization (PSO). These results show that the Firefly Algorithm (FA) tracks the MPP accurately compared with other above mentioned techniques. The PV system performance parameters i.e., convergence and tracking speed, is improved compared to conventional MPP tracking (MPPT) algorithms. It accurately tracks the various situations that outperform other methods. The proposed method significantly increased tracking efficiency and maximized the amount of energy recovered from PV arrays. Results show that FA exhibits high tracking efficiency (>99%) and less convergence time (<0.05 s) under PSCs with less power oscillations. All of these methods have been validated in Matlab simulation software

Performance analysis of high throughput MAP decoder for turbo codes and self concatenated convolutional codes

The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed for mitigating the BER degradation resulting from increased parallelism. In order to analyze and compare the architectural performance of both schemes, this paper presents the Very High Speed Integrated Circuit Hardware Description Language (VHDL) design of Maximum Aposteriori Probability (MAP) decoder for TC and SECCC, both employing the same constituent code. The simulation results show that for BER of 10−4, without parallelism, TC is 0.4 dB superior to SECCC, whereas, with parallelism of 64, the difference in performance between both schemes reduces to 0.25 dB. It is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64. The BER performance of both schemes shows that SECCC outperforms TC at parallelism of 256 by 0.3 dB at BER of 10−4. Hence, for high throughput architectures employing higher parallelism (beyond 64 and 128) without significant degradation in BER performance, SECCC performs better than TC. The synthesis results of VHDL design of the MAP decoder obtained using Xilinx ISE verify that both schemes have equal clock frequency and resource consumption. It is demonstrated that the MAP decoder achieves the clock frequency of 86.3 MHz which is capable of producing a throughput of 691 Mbps using parallelism of 64