A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications

This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and power management strategies cannot be correctly established without accounting for the associated overhead related to the DC-DC converters that provide regulated power to the system. The proposed model accurately predicts the efficiency of inductor based DC-DC converters with varying topologies and control schemes across a range of output voltage and current loads. It also accounts for the energy and timing overhead associated with the change in the operating condition of the regulator. Since modern SoCs employ power management techniques that vary the voltage and current loads seen by the converter, accurate modeling of the impact on the converter efficiency becomes critical. We use this model to compute the overall cost of two power distribution strategies for a SoC with multiple voltage islands. The proposed model helps us to obtain the energy benefits of a power management technique and can also be used as a basis for comparison between power management techniques or as a tool for design space exploration early in a SoC design cycle

A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs

This paper presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter supports energy harvesting systems that need to use very low voltages

A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications

We propose a fully on-chip CMOS temperature sensor in which a sub-threshold (sub-VT) proportional-to-absolute-temperature (PTAT) current element starves a current-controlled oscillator (CCO). Sub-VT design enables ultra-low-power operation of this temperature sensor. However, such circuits are highly sensitive to process variations, thereby causing varying circuit currents from die to die. We propose a bit-weighted current mirror (BWCM) architecture to resist the effect of process-induced variation in the PTAT current. The analog core constituting the PTAT, the CCO, and the BWCM is operational down to 0.2 V supply voltage. A digital block operational at 0.5 V converts the temperature information into a digital code that can be processed and used by other components in a system-on-chip (SoC). The proposed temperature sensor system also supports resolution-power trade-off for Internet-of-things (IoT) applications with different sampling rates and energy needs. The system power consumption is 23 nW and the maximum temperature inaccuracy is +1.5/−1.7 °C from 0 °C to 100 °C with a two-point calibration. The temperature sensor system was designed in a 130 nm CMOS technology and its total area is 250 × 250 μm2

A 36 nW, 7 ppm/°C on-Chip Clock Source Platform for Near-Human-Body Temperature Applications

We propose a fully on-chip clock-source system in which an ultra-low-power diode-based temperature-uncompensated oscillator (OSC[ subscript diode]) serves as the main clock source and frequency locks to a higher-power temperature-compensated oscillator (OSC[subscript cmp]) that is disabled after each locking event to save power. The locking allows the stability of the uncompensated oscillator to stay within the stability bound of the compensated design. This paper demonstrates the functionality of a locking controller that uses a periodic (counter-based) scheme implemented on-chip and a prediction (temperature-drift-based) scheme. The flexible clock source platform is validated in a 130 nm CMOS technology. In the demonstrated system, it achieves an effective average temperature stability of 7 ppm/°C in the human body temperature range from 20 °C to 40 °C with a power consumption of 36 nW at 0.7 V. It achieves a frequency range of 12 kHz to 150 kHz at 0.7 V.Charles Stark Draper Laborator

A Radio Frequency Magnetoelectric Antenna Prototyping Platform for Neural Activity Monitoring Devices with Sensing and Energy Harvesting Capabilities

This article describes the development of a radio frequency (RF) platform for electromagnetically modulated signals that makes use of a software-defined radio (SDR) to receive information from a novel magnetoelectric (ME) antenna capable of sensing low-frequency magnetic fields with ultra-low magnitudes. The platform is employed as part of research and development to utilize miniaturized ME antennas and integrated circuits for neural recording with wireless implantable devices. To prototype the reception of electromagnetically modulated signals from a sensor, a versatile Universal Software Radio Peripheral (USRP) and the GNU Radio toolkit are utilized to enable real-time signal processing under varying operating conditions. Furthermore, it is demonstrated how a radio frequency signal transmitted from the SDR can be captured by the ME antenna for wireless energy harvesting

Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices

A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms